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authorBas Nieuwenhuizen <[email protected]>2018-01-04 02:11:51 +0100
committerBas Nieuwenhuizen <[email protected]>2018-01-04 19:35:36 +0100
commit76daa30e4a0d3dfe04c5b79fcdfba17fb1656ccd (patch)
treef78635ef076cf4db6530389e5da75ef55591a048 /doxygen
parentf2c9f13ec2fdab99f5aa7f32845ee94dd1942fe9 (diff)
radv: Use correct flush bits for flushing L2 during CB/DB flushes.
Copied from radeonsi. Putting in the correct metadata flush commands for eventually not flushing L2 on CB/DB switch. Does not remove the need for V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT at the moment. Reviewed-by: Samuel Pitoiset <[email protected]>
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