diff options
| author | Tom Stellard <[email protected]> | 2012-08-31 16:11:38 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-09-04 14:21:10 -0400 |
| commit | f9fede884b7ace711ccf63152afdbdaf209edced (patch) | |
| tree | f6a299809e87115eb037e3a85da382bc3a13c34c /doxygen/radeon_subset.doxy | |
| parent | f73ffacbf0c65ad843406af37aa35e9112bc8038 (diff) | |
radeon/llvm: Fix encoding of V_CNDMASK_B32
The CodeEmitter was not setting the VGPR bit for src0, because the
instruction definition had the VCC register in the src0 slot, instead of
the actual src0 register. This has been fixed by moving the VCC
register to the end of the operand list.
Diffstat (limited to 'doxygen/radeon_subset.doxy')
0 files changed, 0 insertions, 0 deletions