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authorMarek Olšák <[email protected]>2017-06-05 19:59:06 +0200
committerMarek Olšák <[email protected]>2017-06-07 19:38:42 +0200
commit66176e6f14269937f64225d94779e0592eed6a1e (patch)
treee8bac5103c7e9c6504de92b49bc95fe41b95e8cc /docs
parentd2ee423b69660a219c031abad101decd0ecae327 (diff)
radeonsi: don't use 1D tiling for Z/S on VI to get TC-compatible HTILE
It's always good to have fewer decompress blits. Reviewed-by: Nicolai Hähnle <[email protected]>
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