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author | Rob Clark <[email protected]> | 2013-12-20 20:48:18 -0500 |
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committer | Rob Clark <[email protected]> | 2013-12-26 12:06:29 -0500 |
commit | be01d7a905d827c3c0c222cab2430c6d4575429a (patch) | |
tree | fc714be776c88076f061280b60137c1322af103b /docs/perf.html | |
parent | 64fe0670664bc6f2c75cc1630aa07cef1898b8b5 (diff) |
freedreno: prepare for hw binning
Actually assign VSC_PIPE's properly, which will be needed for tiling.
And introduce fd_tile for per-tile state (including the assignment of
tile to VSC_PIPE). This gives us the proper pipe setup that we'll
need for hw binning pass, and also cleans things up a bit by not having
to pass so many parameters around. And will also make it easier to
introduce different tiling patterns (since we may no longer render
tiles in a simple left-to-right top-to-bottom pattern).
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'docs/perf.html')
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