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| author | Marek Olšák <[email protected]> | 2017-02-27 22:25:44 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-04-04 11:14:43 +0200 |
| commit | 18e760346aab10affd6e9ff129f800d90fa28456 (patch) | |
| tree | 675c8774069880cd1d0f5ba1523e255071d9069b /docs/perf.html | |
| parent | 3e7d62a774c2598f308e612507672136886ebe60 (diff) | |
amd/addrlib: second update for Vega10 + bug fixes
Highlights:
- Display needs tiled pitch alignment to be at least 32 pixels
- Implement Addr2ComputeDccAddrFromCoord().
- Macro-pixel packed formats don't support Z swizzle modes
- Pad pitch and base alignment of PRT + TEX1D to 64KB.
- Fix support for multimedia formats
- Fix a case "PRT" entries are not selected on SI.
- Fix wrong upper bits in equations for 3D resource.
- We can't support 2d array slice rotation in gfx8 swizzle pattern
- Set base alignment for PRT + non-xor swizzle mode resource to 64KB.
- Bug workaround for Z16 4x/8x and Z32 2x/4x/8x MSAA depth texture
- Add stereo support
- Optimize swizzle mode selection
- Report pitch and height in pixels for each mip
- Adjust bpp/expandX for format ADDR_FMT_GB_GR/ADDR_FMT_BG_RG
- Correct tcCompatible flag output for mipmap surface
- Other fixes and cleanups
Acked-by: Alex Deucher <[email protected]>
Acked-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'docs/perf.html')
0 files changed, 0 insertions, 0 deletions