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| author | Matt Turner <[email protected]> | 2017-06-14 11:03:19 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2018-02-28 11:15:47 -0800 |
| commit | 2cff3242109078999c57d5e6772418c09e835826 (patch) | |
| tree | 2a039fe05a88b4737fa7a88371a87eb5ec493bde /docs/lists.html | |
| parent | 58611ff913df74e7f790b0c572b983a992e25a17 (diff) | |
intel/compiler: Add Gen11+ native float type
This new type exposes the additional precision offered by the
accumulator register and will be used in the next patch to implement the
functionality of the PLN instruction using a pair of MAD instructions.
One weird thing to note: align1 ternary instructions may only have an
accumulator in the dst or src1 normally, but when src0's type is :NF
the accumulator is read.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'docs/lists.html')
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