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| author | Francisco Jerez <[email protected]> | 2019-08-05 18:21:05 -0700 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2019-10-11 12:24:16 -0700 |
| commit | 152754665abb937a49e451331c88266ef5c3cdf1 (patch) | |
| tree | e3c73025b48a4026eabc6a581cbea08ea2b10141 /common.py | |
| parent | c344c92b31454115261d6f235d00e4e14ed0ce3c (diff) | |
intel/ir: Represent logical edge of BREAK instruction.
Currently only the physical back-edge is represented, which
incidentally also leads to the exit block of the loop, but we need the
direct logical edge in addition for our logical CFG representation to
be complete.
Reviewed-by: Jordan Justen <[email protected]>
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Diffstat (limited to 'common.py')
0 files changed, 0 insertions, 0 deletions