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| author | Dave Airlie <[email protected]> | 2017-10-19 04:52:29 +0100 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-10-19 23:56:48 +0100 |
| commit | c8eb3558cc246ecd053ff50191f94f1535013688 (patch) | |
| tree | e8a0f3e1e4a01628928262536f08aa7908e28830 /common.py | |
| parent | a447f9fe7b7902db6f91bd4b24adb4ddfad4b10b (diff) | |
radv: fix CLEAR_STATE packet length.
Looking at shader traces I noticed some registers were missing,
one of them was being eaten by the wrong clear state length.
Fixes: 4f42ea4dc (radv: use CLEAR_STATE for initializing some registers)
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'common.py')
0 files changed, 0 insertions, 0 deletions