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authorNanley Chery <[email protected]>2019-08-30 14:16:54 -0700
committerNanley Chery <[email protected]>2019-10-28 10:47:05 -0700
commitba52cd7ab2a6908eb198307186e9c5ece004450a (patch)
tree48d27bbf8b77af372c52dcaed73e902773b36d66 /bin/perf-annotate-jit.py
parent4021a3925c780643e0b402c5b20ddf7b6b780c09 (diff)
intel/blorp: Don't assert aux slices match main slices
This isn't accurate enough for HiZ which can have a discontiguous range of supported aux slices. This also won't work with the plan to represent Gen12 CCS as a single slice surface. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
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