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| author | Iago Toral Quiroga <[email protected]> | 2017-09-07 12:56:27 +0200 |
|---|---|---|
| committer | Iago Toral Quiroga <[email protected]> | 2017-09-12 08:09:45 +0200 |
| commit | ab6f874439943837c06d3346385f75145e6d2775 (patch) | |
| tree | eb551003af702e8d16bc40be37c6376f8ff5f3f6 /bin/git_sha1_gen.py | |
| parent | 806ae6a648326327ead48d1b9aec6f44f74f06f9 (diff) | |
i965: do not fallback to linear tiling for stencil surfaces
We were skipping this fallback for depth, but not for stencil
which the hardware always requires to be W-tiled.
Also, make the checks for whether we need to apply retiling
strategies based on usage instead of tiling flags, which is
safer and more explicit.
This fixes a regression in a CTS test introduced with commit
4ea63fab77f0 that started applying re-tiling stencil surfaces
in certain scenarios.
v2: discard retiling based on usage fields instead of tiling
flags. This is safer and more explicit.
v3: Add a comment indicating that texturing of stencil in gen7
requires an Y-tiled copy (Topi).
Fixes:
KHR-GL45.direct_state_access.renderbuffers_storage
Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'bin/git_sha1_gen.py')
0 files changed, 0 insertions, 0 deletions