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author | Ilia Mirkin <[email protected]> | 2019-02-02 02:56:48 -0500 |
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committer | Ilia Mirkin <[email protected]> | 2019-02-06 19:35:57 -0500 |
commit | 5de5beedf21306b01730085f8e03d8f424729016 (patch) | |
tree | d15d9f6592b14508f7a5141dade370524e9548f4 /appveyor.yml | |
parent | 4443b6ddf2e08d06f3d0457cf20a2e04244cde37 (diff) |
nvc0/ir: fix second tex argument after levelZero optimization
We used to pre-set a bunch of extra arguments to a texture instruction
in order to force the RA to allocate a register at the boundary of 4.
However with the levelZero optimization, which removes a LOD argument
when it's uniformly equal to zero, we undid that logic by removing an
extra argument. As a result, we could end up with insufficient alignment
on the second wide texture argument.
Instead we switch to a different method of achieving the same result.
The logic runs during the constraint analysis of the RA, and adds unset
sources as necessary right before being merged into a wide argument.
Fixes MISALIGNED_REG errors in Hitman when run with bindless textures
enabled on a GK208.
Fixes: 9145873b152 ("nvc0/ir: use levelZero flag when the lod is set to 0")
Signed-off-by: Ilia Mirkin <[email protected]>
Cc: 19.0 <[email protected]>
Diffstat (limited to 'appveyor.yml')
0 files changed, 0 insertions, 0 deletions