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| author | Francisco Jerez <[email protected]> | 2016-05-27 23:29:02 -0700 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2016-05-27 23:29:02 -0700 |
| commit | 1e3c58ffaf35c6d37284b53c7b742c1bf7f2e67c (patch) | |
| tree | 5ebdad6fc84e76fe1138445ff71610dd99bdb2df /VERSION | |
| parent | a7d319c00be425be219a101b5b4d48f1cbe4ec01 (diff) | |
i965/fs: Lower 32-wide scratch writes in the generator.
The hardware has messages that can write 32 32bit components at once
but the channel enable mask gets messed up. We need to split them
into several 16-wide scratch writes for the channel enables to be
applied correctly. The SIMD lowering pass cannot be used for this
because scratch writes are emitted rather late during register
allocation long after SIMD lowering has been done.
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'VERSION')
0 files changed, 0 insertions, 0 deletions