i965: Add a new infrastructure for generating Broadwell shader assembly.

This replaces the brw_eu_emit.c layer for Broadwell.  It will be
used by both the vector and scalar shader backends.

v2: Port to use the C-based instruction representation.

v3: Fix destination register type for CMP.

v4: Pass brw to gen8_instruction functions (required by rebase).

v5: Remove bogus assertion on math instructions (caught by Piglit).

v6: Remove more restrictions on math instructions (caught by Eric).
    Make ADDC and SUBB helpers set accumulator writes, like MAC and
    MACH (caught by Matt).

v7: Don't implicitly force ALU3 operations to SIMD8 (we've been able
    to do SIMD16 versions since Haswell, but didn't when I originally
    wrote this code).

Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Matt Turner <[email protected]>

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