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authorIago Toral Quiroga <itoral@igalia.com>2016-05-24 11:01:27 +0200
committerSamuel Iglesias Gonsálvez <siglesias@igalia.com>2017-01-03 11:26:51 +0100
commite238601a2da9512c0fd263e8378f30498a0a1507 (patch)
treebb9232a19b2b8e292dc960e67907d71ec22985f8 /SConstruct
parentfb7cb853c964db44ab99c1592e1ef7dec2f0c25b (diff)
i965/vec4: translate 64-bit swizzles to 32-bit
The hardware can only operate with 32-bit swizzles, which is a rather limiting restriction. However, the idea is not to expose this to the optimization passes, which would be a mess to deal with. Instead, we let the bulk of the vec4 backend ignore this fact and we fix the swizzles right at codegen time. At the moment the pass only needs to handle single value swizzles thanks to the scalarization pass that runs before it. Notice that this only works for X/Y swizzles. We will add support for Z/W swizzles in the next patch, since they need a bit more work. v2 (Sam): - Do not expand swizzle of 64-bit immediate values. v3: - Do this after translation to hardware registers instead of doing it right before so we don't need the force_vstride0 flag (Curro). - Squashed patch that included FIXED_GRF in the list of register files that need this translation (Iago). - Remove swizzle assignments for VGRF and UNIFORM files in convert_to_hw_regs(), they will be set by apply_logical_swizzle() (Iago). Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
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