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authorDave Airlie <[email protected]>2017-12-27 11:22:58 +1000
committerDave Airlie <[email protected]>2017-12-28 05:23:49 +1000
commit5ba26ed6e5aca41d285613ce8d29fed032db87a9 (patch)
treef886c4feab3277ec569f4649c843c790d51c5028 /CleanSpec.mk
parent3e59e442c3a668628bc780a6834059ed69afacb2 (diff)
radv/gfx9: use correct stencil format for tc compat htile.
This needs to correspond to the bit depth of the Z plane. noticed in passing reading amdvlk. Fixes: fc6c77e162df3 (radv: fix TC-compat HTILE with VK_FORMAT_D32_SFLOAT_S8_UINT on Vega) Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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