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authorEric Anholt <[email protected]>2015-12-22 13:37:36 -0800
committerEric Anholt <[email protected]>2016-01-06 12:39:51 -0800
commit71db7d3dc577e48da3689fd66989ec3b0a069089 (patch)
tree450fb776d1617cbdec4160d81a87480599c7dbb1 /CleanSpec.mk
parent0a89f307f95de3a3357d834f36c60fe803895f8a (diff)
vc4: Replace the SSA-style SEL operators with conditional MOVs.
I'm moving away from QIR being SSA (since NIR is doing lots of SSA optimization for us now) and instead having QIR just be QPU operations with virtual registers. By making our SELs be composed of two MOVs, we could potentially coalesce the registers for the MOV's src and dst and eliminate the MOV. total instructions in shared programs: 88448 -> 88028 (-0.47%) instructions in affected programs: 39845 -> 39425 (-1.05%) total estimated cycles in shared programs: 246306 -> 245762 (-0.22%) estimated cycles in affected programs: 162887 -> 162343 (-0.33%)
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