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authorNanley Chery <[email protected]>2017-03-07 11:17:05 -0800
committerNanley Chery <[email protected]>2017-03-20 09:43:44 -0700
commit7c50f9903f58ef04ff393505a383d06f499f1fdc (patch)
tree4ece2ce95847ba8ab4465526531da36f1e0995a0
parentf4b23589da8ad395b6d5bc968502d8128a8bd8c5 (diff)
intel: Correct the BDW surface state size
The PRMs state that this packet is 16 DWORDS long. Ensure that the last three DWORDS are zeroed as required by the hardware when allocating a null surface state. Cc: <[email protected]> Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
-rw-r--r--src/intel/isl/isl.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen8_surface_state.c5
2 files changed, 3 insertions, 4 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 6eb1e93efd9..b4bdf2059ac 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -56,7 +56,7 @@ static const struct {
[5] = {24, 32, 4},
[6] = {24, 32, 4},
[7] = {32, 32, 4, 24},
- [8] = {52, 64, 32, 40},
+ [8] = {64, 64, 32, 40},
[9] = {64, 64, 32, 40},
};
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 501531d4ad4..f8682932172 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -46,10 +46,9 @@ static uint32_t *
gen8_allocate_surface_state(struct brw_context *brw,
uint32_t *out_offset, int index)
{
- int dwords = brw->gen >= 9 ? 16 : 13;
uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- dwords * 4, 64, index, out_offset);
- memset(surf, 0, dwords * 4);
+ 64, 64, index, out_offset);
+ memset(surf, 0, 64);
return surf;
}