diff options
| author | Brian Ho <[email protected]> | 2020-04-03 11:53:55 -0700 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-04-03 19:44:46 +0000 |
| commit | 6e7645347288c7dd8a4b95d69a4617278aa7b7c3 (patch) | |
| tree | 99c3c80639f189891346e44461d60e3756246680 | |
| parent | ea51f8f79ac43ff00d78cd53266f92125b2d5fd4 (diff) | |
ir3: Disable copy prop for immediate ldlw offsets
Immediate offsets are currently collapsed for ldlw, but ldlw does
behave correctly with immediate values. For example,
`ldlw.u32 r0.x, l[4], 1` actually means to use the value of
regid 4 (r1.x) as the offset when we actually want it to use the
imm value of 4 as the offset.
This commit disables copy prop for ldlw offsets so the same
intrinsic gets compiled to:
mov.u32u32 r0.y, 0x00000004
ldlw.u32 r0.x, l[r0.y], 1
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4439>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4439>
| -rw-r--r-- | src/freedreno/ir3/ir3_cp.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/freedreno/ir3/ir3_cp.c b/src/freedreno/ir3/ir3_cp.c index 14a5ae8d06c..5cac9c6b2d4 100644 --- a/src/freedreno/ir3/ir3_cp.c +++ b/src/freedreno/ir3/ir3_cp.c @@ -229,6 +229,9 @@ static bool valid_flags(struct ir3_instruction *instr, unsigned n, if (instr->opc == OPC_STLW && n == 0) return false; + if (instr->opc == OPC_LDLW && n == 0) + return false; + /* disallow CP into anything but the SSBO slot argument for * atomics: */ |