intel: Implement Gen12 workaround for array textures of size 1

Gen12 does not support RENDER_SURFACE_STATE::SurfaceArray = true &&
RENDER_SURFACE_STATE::Depth = 0. SurfaceArray can only be set to true
if Depth >= 1.

We workaround this limitation by adding the max(value, 1) snippet in
the shaders on the 3 components for texture array sizes.

Tested on Gen9 with the following Vulkan CTS tests :
dEQP-VK.image.image_size.2d_array.*

v2: Drop debug print (Tapani)
    Switch to GEN:BUG instead of Wa_

v3: Fix dEQP-VK.image.image_size.1d_array.* cases (Lionel)

v4: Fix dEQP-VK.glsl.texture_functions.query.texturesize.* cases
    (Missing tex_op handling) (Lionel)

v5: Missing break statement (Lionel)

v6: Fixup comment (Tapani)

v7: Fixup comment again (Tapani)

v8: Don't use sample_dim as index (Jason)
    Rename pass
    Simplify control flow

Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]> (v7)
Reviewed-by: Jason Ekstrand <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3362>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3362>

6 files changed, 151 insertions, 1 deletions

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 252a0cb5320..d956475456b 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -84,6 +84,7 @@ COMPILER_FILES = \
 	compiler/brw_nir.c \
 	compiler/brw_nir_analyze_boolean_resolves.c \
 	compiler/brw_nir_analyze_ubo_ranges.c \
+	compiler/brw_nir_clamp_image_1d_2d_array_sizes.c \
 	compiler/brw_nir_attribute_workarounds.c \
 	compiler/brw_nir_lower_alpha_to_coverage.c \
 	compiler/brw_nir_lower_conversions.c \
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index e29398db7f6..c5646ebd509 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -665,6 +665,9 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
        !(devinfo->gen >= 10 || devinfo->is_kabylake))
       OPT(brw_nir_apply_trig_workarounds);
 
+   if (devinfo->gen >= 12)
+      OPT(brw_nir_clamp_image_1d_2d_array_sizes);
+
    static const nir_lower_tex_options tex_options = {
       .lower_txp = ~0,
       .lower_txf_offset = true,
diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h
index 7c7f1ea11b7..32a8badaa24 100644
--- a/src/intel/compiler/brw_nir.h
+++ b/src/intel/compiler/brw_nir.h
@@ -134,6 +134,8 @@ void brw_postprocess_nir(nir_shader *nir,
                          const struct brw_compiler *compiler,
                          bool is_scalar);
 
+bool brw_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader);
+
 bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
                                          const uint8_t *attrib_wa_flags);
 
diff --git a/src/intel/compiler/brw_nir_clamp_image_1d_2d_array_sizes.c b/src/intel/compiler/brw_nir_clamp_image_1d_2d_array_sizes.c
new file mode 100644
index 00000000000..d77955a2d54
--- /dev/null
+++ b/src/intel/compiler/brw_nir_clamp_image_1d_2d_array_sizes.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "compiler/nir/nir_builder.h"
+#include "brw_nir.h"
+
+/**
+ * GEN:BUG:1806565034:
+ *
+ * Gen12+ allows to set RENDER_SURFACE_STATE::SurfaceArray to 1 only if
+ * array_len > 1. Setting RENDER_SURFACE_STATE::SurfaceArray to 0 results in
+ * the HW RESINFO message to report an array size of 0 which breaks texture
+ * array size queries.
+ *
+ * This NIR pass works around this by patching the array size with a
+ * MAX(array_size, 1) for array textures.
+ */
+
+bool
+brw_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader)
+{
+   bool progress = false;
+   nir_builder b;
+
+   nir_foreach_function(func, shader) {
+      bool function_progress = false;
+
+      if (!func->impl)
+         continue;
+
+      nir_builder_init(&b, func->impl);
+
+      nir_foreach_block(block, func->impl) {
+         nir_foreach_instr_safe(instr, block) {
+            nir_ssa_def *image_size = NULL;
+
+            switch (instr->type) {
+            case nir_instr_type_intrinsic: {
+               nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
+
+               switch (intr->intrinsic) {
+               case nir_intrinsic_image_size:
+               case nir_intrinsic_bindless_image_size:
+                  if (!nir_intrinsic_image_array(intr))
+                     break;
+
+                  image_size = &intr->dest.ssa;
+                  break;
+
+               case nir_intrinsic_image_deref_size: {
+                  nir_deref_instr *deref = nir_src_as_deref(intr->src[0]);
+
+                  assert(glsl_type_is_image(deref->type));
+
+                  if (!glsl_sampler_type_is_array(deref->type))
+                     break;
+
+                  image_size = &intr->dest.ssa;
+                  break;
+               }
+
+               default:
+                  break;
+               }
+               break;
+            }
+
+            case nir_instr_type_tex: {
+               nir_tex_instr *tex_instr = nir_instr_as_tex(instr);
+               if (tex_instr->op != nir_texop_txs)
+                  break;
+
+               if (!tex_instr->is_array)
+                  break;
+
+               image_size = &tex_instr->dest.ssa;
+               break;
+            }
+
+            default:
+               break;
+            }
+
+            if (!image_size)
+               continue;
+
+            b.cursor = nir_after_instr(instr);
+
+            nir_ssa_def *components[4];
+            for (int i = 0; i < image_size->num_components; i++) {
+               if (i == (image_size->num_components - 1)) {
+                  components[i] = nir_imax(&b, nir_channel(&b, image_size, i),
+                                               nir_imm_int(&b, 1));
+               } else {
+                  components[i] = nir_channel(&b, image_size, i);
+               }
+            }
+            nir_ssa_def *image_size_replacement =
+               nir_vec(&b, components, image_size->num_components);
+
+            b.cursor = nir_after_instr(instr);
+
+            nir_ssa_def_rewrite_uses_after(image_size,
+                                           nir_src_for_ssa(image_size_replacement),
+                                           image_size_replacement->parent_instr);
+
+            function_progress = true;
+         }
+      }
+
+      if (function_progress) {
+         nir_metadata_preserve(func->impl, nir_metadata_block_index |
+                                           nir_metadata_dominance);
+         progress = function_progress;
+      }
+   }
+
+   return progress;
+}
diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build
index 3b144561372..4a4a76cece8 100644
--- a/src/intel/compiler/meson.build
+++ b/src/intel/compiler/meson.build
@@ -83,6 +83,7 @@ libintel_compiler_files = files(
   'brw_nir_lower_mem_access_bit_sizes.c',
   'brw_nir_opt_peephole_ffma.c',
   'brw_nir_tcs_workarounds.c',
+  'brw_nir_clamp_image_1d_2d_array_sizes.c',
   'brw_packed_float.c',
   'brw_predicated_break.cpp',
   'brw_reg.h',
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index f1d55686797..c66f09b4b68 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -402,7 +402,11 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
       unreachable("bad SurfaceType");
    }
 
-#if GEN_GEN >= 7
+#if GEN_GEN >= 12
+   /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */
+   s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
+      info->view->array_len > 1;
+#elif GEN_GEN >= 7
    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 #endif