diff options
author | Ian Romanick <[email protected]> | 2018-06-14 15:26:58 -0700 |
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committer | Ian Romanick <[email protected]> | 2018-06-15 17:22:27 -0700 |
commit | e6a9bd97b97a303463db3eeae38fed61c43c44b1 (patch) | |
tree | 93f39deb17a9d1454fae49dee19aa1b45c6296e7 | |
parent | 284b563fb0689f8c51aae45ad9e331ba4b776ddf (diff) |
i965/vec4: Don't register coalesce into source of VS_OPCODE_UNPACK_FLAGS_SIMD4X2
This prevents regressions in a bunch of clipping and interpolation tests
caused by the next patch (i965/vec4: Optimize OR with 0 into a MOV).
Signed-off-by: Ian Romanick <[email protected]>
-rw-r--r-- | src/intel/compiler/brw_vec4.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 4464a913988..e67d7802550 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -1285,6 +1285,15 @@ vec4_visitor::opt_register_coalesce() } } + /* VS_OPCODE_UNPACK_FLAGS_SIMD4X2 generates a bunch of mov(1) + * instructions, and this optimization pass is not capable of + * handling that. Bail on these instructions and hope that some + * later optimization pass can do the right thing after they are + * expanded. + */ + if (scan_inst->opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2) + break; + /* This doesn't handle saturation on the instruction we * want to coalesce away if the register types do not match. * But if scan_inst is a non type-converting 'mov', we can fix |