diff options
| author | Nanley Chery <[email protected]> | 2018-07-16 15:42:39 -0700 |
|---|---|---|
| committer | Nanley Chery <[email protected]> | 2018-07-19 11:05:07 -0700 |
| commit | e2e32b6afd4cd1cd091877b638288e861a537760 (patch) | |
| tree | 2fa802bd24029ce1e561a5dc9add539e49de9580 | |
| parent | 44ab26d0c9bd95f8d15ead5b92f743ee13296aef (diff) | |
intel/isl/gen4: Make depth/stencil buffers Y-Tiled
Rendering to a linear depth buffer on gen4 is causing a GPU hang in the
CI system. Until a better explanation is found, assume that errata is
applicable to all gen4 platforms.
Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e
("i965/miptree: Share tiling_flags in miptree_create").
Reported-by: Mark Janes <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107248
Tested-by: Mark Janes <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
| -rw-r--r-- | src/intel/isl/isl_gen4.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/intel/isl/isl_gen4.c b/src/intel/isl/isl_gen4.c index 14706c895a5..a212d0ee0af 100644 --- a/src/intel/isl/isl_gen4.c +++ b/src/intel/isl/isl_gen4.c @@ -51,8 +51,15 @@ isl_gen4_filter_tiling(const struct isl_device *dev, /* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk: * * "The Depth Buffer, if tiled, must use Y-Major tiling" + * + * Errata Description Project + * BWT014 The Depth Buffer Must be Tiled, it cannot be linear. This + * field must be set to 1 on DevBW-A. [DevBW -A,B] + * + * In testing, the linear configuration doesn't seem to work on gen4. */ - *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_Y0_BIT); + *flags &= (ISL_DEV_GEN(dev) == 4 && !ISL_DEV_IS_G4X(dev)) ? + ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | ISL_TILING_LINEAR_BIT); } if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT | |