diff options
| author | Marek Olšák <[email protected]> | 2017-06-20 18:26:12 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-06-22 13:15:27 +0200 |
| commit | db37c0be13e64cce70491d6c6c0090a8f1d3d1d6 (patch) | |
| tree | c350427eef2004b36596bd4cddd727bb553db36a | |
| parent | 920f20f03936dd1f1ffe9445d2c167ed2cac94f4 (diff) | |
radeonsi/gfx9: don't ever flush the TC metadata cache
The closed Vulkan driver doesn't do it either.
Also remove some old comments that aren't useful.
Reviewed-by: Nicolai Hähnle <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 85ceacad80f..332e0c43de8 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -971,22 +971,15 @@ void si_emit_cache_flush(struct si_context *sctx) } /* TC | TC_WB = invalidate L2 data - * TC_MD | TC_WB = invalidate L2 metadata + * TC_MD | TC_WB = invalidate L2 metadata (DCC, etc.) * TC | TC_WB | TC_MD = invalidate L2 data & metadata - * - * The metadata cache must always be invalidated for coherency - * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC) - * - * TC must be invalidated on GFX9 only if the CB/DB surface is - * not pipe-aligned. If the surface is RB-aligned, it might not - * strictly be pipe-aligned since RB alignment takes precendence. */ - tc_flags = EVENT_TC_WB_ACTION_ENA | - EVENT_TC_MD_ACTION_ENA; + tc_flags = 0; /* Ideally flush TC together with CB/DB. */ if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) { tc_flags |= EVENT_TC_ACTION_ENA | + EVENT_TC_WB_ACTION_ENA | EVENT_TCL1_ACTION_ENA; /* Clear the flags. */ |