diff options
| author | Dave Airlie <[email protected]> | 2017-10-23 06:23:29 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-10-23 07:10:29 +1000 |
| commit | da9c3cd3ee5494b43a8ab3f9a3fee95620d9d357 (patch) | |
| tree | 748b7d9d8a755928d3acd8d1e2af2e65846c4743 | |
| parent | 6ce550453f1df64caeb956f215d32da96b89f2b1 (diff) | |
radv/ac/nir: only emit tess factors to storage if tes reads them
Otherwise we just need to write them to the tf ring.
this seems to improve the tessellation demo on Bonarie
~2190->~2230 fps
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
| -rw-r--r-- | src/amd/common/ac_nir_to_llvm.c | 4 | ||||
| -rw-r--r-- | src/amd/common/ac_nir_to_llvm.h | 1 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 1 |
3 files changed, 4 insertions, 2 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 83b49b535c6..360ca81ca89 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -6166,8 +6166,8 @@ write_tess_factors(struct nir_to_llvm_context *ctx) stride - 4, byteoffset, tf_base, 16 + tf_offset, 1, 0, true, false); - //TODO store to offchip for TES to read - only if TES reads them - if (1) { + //store to offchip for TES to read - only if TES reads them + if (ctx->options->key.tcs.tes_reads_tess_factors) { LLVMValueRef inner_vec, outer_vec, tf_outer_offset; LLVMValueRef tf_inner_offset; unsigned param_outer, param_inner; diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h index eecc2cb8d49..9579aeeefef 100644 --- a/src/amd/common/ac_nir_to_llvm.h +++ b/src/amd/common/ac_nir_to_llvm.h @@ -55,6 +55,7 @@ struct ac_tcs_variant_key { struct ac_vs_variant_key vs_key; unsigned primitive_mode; unsigned input_vertices; + uint32_t tes_reads_tess_factors:1; }; struct ac_fs_variant_key { diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index f23afa42b70..669d9a4858e 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1773,6 +1773,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline, if (keys) keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode; + keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER)); nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out); } |