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authorRob Clark <[email protected]>2015-09-15 17:25:47 -0400
committerRob Clark <[email protected]>2015-09-15 17:29:01 -0400
commitd85267c4bb5416dc3fbac7798b4bb68247340508 (patch)
tree4c48f2cbeb878de1c107a4930138cb7da5c832c5
parentf8222724f539b9e16affc0f4ddd95cfda27293a5 (diff)
freedreno/a4xx: border-color support
Signed-off-by: Rob Clark <[email protected]>
-rw-r--r--src/gallium/drivers/freedreno/a4xx/fd4_context.c5
-rw-r--r--src/gallium/drivers/freedreno/a4xx/fd4_context.h5
-rw-r--r--src/gallium/drivers/freedreno/a4xx/fd4_emit.c20
-rw-r--r--src/gallium/drivers/freedreno/a4xx/fd4_texture.c3
4 files changed, 31 insertions, 2 deletions
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_context.c b/src/gallium/drivers/freedreno/a4xx/fd4_context.c
index 625512ccd1b..e53e0c56c9a 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_context.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_context.c
@@ -55,6 +55,8 @@ fd4_context_destroy(struct pipe_context *pctx)
pipe_resource_reference(&fd4_ctx->solid_vbuf, NULL);
pipe_resource_reference(&fd4_ctx->blit_texcoord_vbuf, NULL);
+ u_upload_destroy(fd4_ctx->border_color_uploader);
+
fd_context_destroy(pctx);
}
@@ -169,5 +171,8 @@ fd4_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
fd4_query_context_init(pctx);
+ fd4_ctx->border_color_uploader = u_upload_create(pctx, 4096,
+ 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, 0);
+
return pctx;
}
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_context.h b/src/gallium/drivers/freedreno/a4xx/fd4_context.h
index af9475699db..074c5a752bf 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_context.h
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_context.h
@@ -29,6 +29,8 @@
#ifndef FD4_CONTEXT_H_
#define FD4_CONTEXT_H_
+#include "util/u_upload_mgr.h"
+
#include "freedreno_drmif.h"
#include "freedreno_context.h"
@@ -70,6 +72,9 @@ struct fd4_context {
*/
struct fd_vertex_state blit_vbuf_state;
+ struct u_upload_mgr *border_color_uploader;
+ struct pipe_resource *border_color_buf;
+
/* if *any* of bits are set in {v,f}saturate_{s,t,r} */
bool vsaturate, fsaturate;
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index b75be29e523..5f36cef3e9a 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -124,7 +124,20 @@ static void
emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
enum adreno_state_block sb, struct fd_texture_stateobj *tex)
{
- unsigned i;
+ static const uint32_t bcolor_reg[] = {
+ [SB_VERT_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
+ [SB_FRAG_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
+ };
+ struct fd4_context *fd4_ctx = fd4_context(ctx);
+ unsigned i, off;
+ void *ptr;
+
+ u_upload_alloc(fd4_ctx->border_color_uploader,
+ 0, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, &off,
+ &fd4_ctx->border_color_buf,
+ &ptr);
+
+ fd_setup_border_colors(tex, ptr, 0);
if (tex->num_samplers > 0) {
int num_samplers;
@@ -190,6 +203,11 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, 0x00000000);
}
}
+
+ OUT_PKT0(ring, bcolor_reg[sb], 1);
+ OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
+
+ u_upload_unmap(fd4_ctx->border_color_uploader);
}
/* emit texture state for mem->gmem restore operation.. eventually it would
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
index 5ee022b30a9..dbff5a738fd 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
@@ -49,12 +49,13 @@ tex_clamp(unsigned wrap, bool clamp_to_edge)
return A4XX_TEX_REPEAT;
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
return A4XX_TEX_CLAMP_TO_EDGE;
+ case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+ return A4XX_TEX_CLAMP_TO_BORDER;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
/* only works for PoT.. need to emulate otherwise! */
return A4XX_TEX_MIRROR_CLAMP;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
return A4XX_TEX_MIRROR_REPEAT;
- case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
case PIPE_TEX_WRAP_MIRROR_CLAMP:
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
/* these two we could perhaps emulate, but we currently