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authorMichel Dänzer <[email protected]>2012-09-06 18:14:22 +0200
committerMichel Dänzer <[email protected]>2012-09-17 18:02:01 +0200
commit97d3d25e1ce137557ebac82410e57219f92c0191 (patch)
treee9f16e5acd2dd975ed939a71466fb9247ce72fd0
parent39fb7faf959a808f73bf3b27f4bafd1613e76f13 (diff)
radeon/llvm: Match AMDGPUfract on SI.
Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
-rw-r--r--src/gallium/drivers/radeon/SIInstructions.td4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index 4b76dad0eec..b221d6d07ff 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -524,7 +524,9 @@ defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>;
//defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>;
//defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>;
-defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", []>;
+defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
+ [(set VReg_32:$dst, (AMDGPUfract AllReg_32:$src0))]
+>;
defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", []>;
defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", []>;
defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",