diff options
| author | Michel Dänzer <[email protected]> | 2012-08-02 17:30:44 +0200 |
|---|---|---|
| committer | Michel Dänzer <[email protected]> | 2012-08-02 18:38:16 +0200 |
| commit | 93b4f1f97ea961f09218c9cf7d928e499f267f58 (patch) | |
| tree | ea02f377982a9f68bc6dab2499c0fd69a22dc45f | |
| parent | daf4254d07328381ed013aac25e25d6021fbfd14 (diff) | |
radeonsi: Handle TGSI DIV opcode.
Signed-off-by: Michel Dänzer <[email protected]>
Reviewed-by: Tom Stellard <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstructions.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 94748b67259..31b9e5ec1c0 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -1088,6 +1088,11 @@ def : Pat < /* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */ def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>; +def : Pat < + (int_AMDGPU_div AllReg_32:$src0, AllReg_32:$src1), + (V_MUL_LEGACY_F32_e32 AllReg_32:$src0, (V_RCP_LEGACY_F32_e32 AllReg_32:$src1)) +>; + /********** ================== **********/ /********** VOP3 Patterns **********/ /********** ================== **********/ |