diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2017-02-20 09:27:17 +0100 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2017-02-21 09:20:03 +0100 |
| commit | 8cff852ae2481245a81854073e366892eb199963 (patch) | |
| tree | 4c8485c36f02b1ac89a59dbea4db1a6e5ce0a2ff | |
| parent | 5241fb0ffbe302db0835268c911d566fa18665b9 (diff) | |
radv: Don't flush at the start of a command buffer.
The preamble flushes now and the rest is the responsibility of the app.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 916906f7766..248e1afa87b 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1693,26 +1693,11 @@ VkResult radv_BeginCommandBuffer( if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) { switch (cmd_buffer->queue_family_index) { case RADV_QUEUE_GENERAL: - /* Flush read caches at the beginning of CS not flushed by the kernel. */ - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE | - RADV_CMD_FLAG_PS_PARTIAL_FLUSH | - RADV_CMD_FLAG_CS_PARTIAL_FLUSH | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_INV_SMEM_L1 | - RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | - RADV_CMD_FLAG_INV_GLOBAL_L2; emit_gfx_buffer_state(cmd_buffer); radv_set_db_count_control(cmd_buffer); - si_emit_cache_flush(cmd_buffer); break; case RADV_QUEUE_COMPUTE: - cmd_buffer->state.flush_bits = RADV_CMD_FLAG_INV_ICACHE | - RADV_CMD_FLAG_CS_PARTIAL_FLUSH | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_INV_SMEM_L1 | - RADV_CMD_FLAG_INV_GLOBAL_L2; si_init_compute(cmd_buffer); - si_emit_cache_flush(cmd_buffer); break; case RADV_QUEUE_TRANSFER: default: |