diff options
author | Jason Ekstrand <[email protected]> | 2017-07-12 17:14:49 -0700 |
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committer | Jason Ekstrand <[email protected]> | 2017-07-17 13:48:38 -0700 |
commit | 766784ef82bcd459cc8667b0ff92dfcb7fe8e317 (patch) | |
tree | f45c65fdd7b60ee9c17c39c00875b6b8b6688203 | |
parent | cbee2d1102c50c631285fda4411bd6abc86c3d66 (diff) |
i965/miptree: Use BO_ALLOC_ZEROED for CCS_E buffers
Reviewed-by: Topi Pohjolainen <[email protected]>
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 |
1 files changed, 13 insertions, 23 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 7b809f321d3..f08c3e343a8 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1847,13 +1847,20 @@ intel_miptree_alloc_ccs(struct brw_context *brw, if (!aux_state) return false; - /* In case of compression mcs buffer needs to be initialised requiring the - * buffer to be immediately mapped to cpu space for writing. Therefore do - * not use the gpu access flag which can cause an unnecessary delay if the - * backing pages happened to be just used by the GPU. + /* When CCS_E is used, we need to ensure that the CCS starts off in a valid + * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)": + * + * "If Software wants to enable Color Compression without Fast clear, + * Software needs to initialize MCS with zeros." + * + * A CCS value of 0 indicates that the corresponding block is in the + * pass-through state which is what we want. + * + * For CCS_D, on the other hand, we don't care as we're about to perform a + * fast-clear operation. In that case, being hot in caches more useful. */ - const uint32_t alloc_flags = - mt->aux_usage == ISL_AUX_USAGE_CCS_E ? 0 : BO_ALLOC_FOR_RENDER; + const uint32_t alloc_flags = mt->aux_usage == ISL_AUX_USAGE_CCS_E ? + BO_ALLOC_ZEROED : BO_ALLOC_FOR_RENDER; mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree", &temp_ccs_surf, alloc_flags, mt); if (!mt->mcs_buf) { @@ -1863,23 +1870,6 @@ intel_miptree_alloc_ccs(struct brw_context *brw, mt->aux_state = aux_state; - /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are - * used for lossless compression which requires similar initialisation - * as multi-sample compression. - */ - if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) { - /* Hardware sets the auxiliary buffer to all zeroes when it does full - * resolve. Initialize it accordingly in case the first renderer is - * cpu (or other none compression aware party). - * - * This is also explicitly stated in the spec (MCS Buffer for Render - * Target(s)): - * "If Software wants to enable Color Compression without Fast clear, - * Software needs to initialize MCS with zeros." - */ - intel_miptree_init_mcs(brw, mt, 0); - } - return true; } |