i915: Remove most of the code under gen >= 4 checks.

Reviewed-by: Kenneth Graunke <[email protected]>

8 files changed, 17 insertions, 162 deletions

diff --git a/src/mesa/drivers/dri/i915/intel_batchbuffer.c b/src/mesa/drivers/dri/i915/intel_batchbuffer.c
index 8c6524e71af..39e46ca3530 100644
--- a/src/mesa/drivers/dri/i915/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i915/intel_batchbuffer.c
@@ -59,16 +59,6 @@ intel_batchbuffer_init(struct intel_context *intel)
 {
    intel_batchbuffer_reset(intel);
 
-   if (intel->gen >= 6) {
-      /* We can't just use brw_state_batch to get a chunk of space for
-       * the gen6 workaround because it involves actually writing to
-       * the buffer, and the kernel doesn't let us write to the batch.
-       */
-      intel->batch.workaround_bo = drm_intel_bo_alloc(intel->bufmgr,
-						      "pipe_control workaround",
-						      4096, 4096);
-   }
-
    if (!intel->has_llc) {
       intel->batch.cpu_map = malloc(intel->maxBatchSize);
       intel->batch.map = intel->batch.cpu_map;
@@ -191,14 +181,7 @@ do_flush_locked(struct intel_context *intel)
    }
 
    if (!intel->intelScreen->no_hw) {
-      int flags;
-
-      if (intel->gen < 6 || !batch->is_blit) {
-	 flags = I915_EXEC_RENDER;
-      } else {
-	 flags = I915_EXEC_BLT;
-      }
-
+      int flags = I915_EXEC_RENDER;
       if (batch->needs_sol_reset)
 	 flags |= I915_EXEC_GEN7_SOL_RESET;
 
@@ -511,50 +494,7 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
 void
 intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
 {
-   if (intel->gen >= 6) {
-      if (intel->batch.is_blit) {
-	 BEGIN_BATCH_BLT(4);
-	 OUT_BATCH(MI_FLUSH_DW);
-	 OUT_BATCH(0);
-	 OUT_BATCH(0);
-	 OUT_BATCH(0);
-	 ADVANCE_BATCH();
-      } else {
-	 if (intel->gen == 6) {
-	    /* Hardware workaround: SNB B-Spec says:
-	     *
-	     * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
-	     * Flush Enable =1, a PIPE_CONTROL with any non-zero
-	     * post-sync-op is required.
-	     */
-	    intel_emit_post_sync_nonzero_flush(intel);
-	 }
-
-	 BEGIN_BATCH(4);
-	 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
-	 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
-		   PIPE_CONTROL_WRITE_FLUSH |
-		   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-                   PIPE_CONTROL_VF_CACHE_INVALIDATE |
-		   PIPE_CONTROL_TC_FLUSH |
-		   PIPE_CONTROL_NO_WRITE |
-                   PIPE_CONTROL_CS_STALL);
-	 OUT_BATCH(0); /* write address */
-	 OUT_BATCH(0); /* write data */
-	 ADVANCE_BATCH();
-      }
-   } else if (intel->gen >= 4) {
-      BEGIN_BATCH(4);
-      OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) |
-		PIPE_CONTROL_WRITE_FLUSH |
-		PIPE_CONTROL_NO_WRITE);
-      OUT_BATCH(0); /* write address */
-      OUT_BATCH(0); /* write data */
-      OUT_BATCH(0); /* write data */
-      ADVANCE_BATCH();
-   } else {
-      BEGIN_BATCH(1);
-      OUT_BATCH(MI_FLUSH);
-      ADVANCE_BATCH();
-   }
+   BEGIN_BATCH(1);
+   OUT_BATCH(MI_FLUSH);
+   ADVANCE_BATCH();
 }
diff --git a/src/mesa/drivers/dri/i915/intel_context.c b/src/mesa/drivers/dri/i915/intel_context.c
index 19d5436bc8b..1f8df318526 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -291,7 +291,6 @@ static const struct dri_debug_control debug_control[] = {
    { "vs",    DEBUG_VS },
    { "clip",  DEBUG_CLIP },
    { "aub",   DEBUG_AUB },
-   { "shader_time", DEBUG_SHADER_TIME },
    { "no16",  DEBUG_NO16 },
    { "blorp", DEBUG_BLORP },
    { NULL,    0 }
@@ -321,8 +320,7 @@ intel_flush_rendering_to_batch(struct gl_context *ctx)
    if (intel->Fallback)
       _swrast_flush(ctx);
 
-   if (intel->gen < 4)
-      INTEL_FIREVERTICES(intel);
+   INTEL_FIREVERTICES(intel);
 }
 
 void
@@ -495,10 +493,6 @@ intelInitContext(struct intel_context *intel,
       intel->is_945 = true;
    }
 
-   if (intel->gen >= 5) {
-      intel->needs_ff_sync = true;
-   }
-
    intel->has_llc = intel->intelScreen->hw_has_llc;
    intel->has_swizzling = intel->intelScreen->hw_has_swizzling;
 
@@ -506,11 +500,8 @@ intelInitContext(struct intel_context *intel,
 	  0, sizeof(ctx->TextureFormatSupported));
 
    driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
-                       sPriv->myNum, (intel->gen >= 4) ? "i965" : "i915");
-   if (intel->gen < 4)
-      intel->maxBatchSize = 4096;
-   else
-      intel->maxBatchSize = BATCH_SZ;
+                       sPriv->myNum, "i915");
+   intel->maxBatchSize = 4096;
 
    /* Estimate the size of the mappable aperture into the GTT.  There's an
     * ioctl to get the whole GTT size, but not one to get the mappable subset.
@@ -552,9 +543,6 @@ intelInitContext(struct intel_context *intel,
    ctx->Const.MaxPointSizeAA = 3.0;
    ctx->Const.PointSizeGranularity = 1.0;
 
-   if (intel->gen >= 6)
-      ctx->Const.MaxClipPlanes = 8;
-
    ctx->Const.StripTextureBorder = GL_TRUE;
 
    /* reinitialize the context point state.
@@ -562,22 +550,9 @@ intelInitContext(struct intel_context *intel,
     */
    _mesa_init_point(ctx);
 
-   if (intel->gen >= 4) {
-      ctx->Const.MaxRenderbufferSize = 8192;
-   } else {
-      ctx->Const.MaxRenderbufferSize = 2048;
-   }
-
-   /* Initialize the software rasterizer and helper modules.
-    *
-    * As of GL 3.1 core, the gen4+ driver doesn't need the swrast context for
-    * software fallbacks (which we have to support on legacy GL to do weird
-    * glDrawPixels(), glBitmap(), and other functions).
-    */
-   if (intel->gen <= 3 || api != API_OPENGL_CORE) {
-      _swrast_CreateContext(ctx);
-   }
+   ctx->Const.MaxRenderbufferSize = 2048;
 
+   _swrast_CreateContext(ctx);
    _vbo_CreateContext(ctx);
    if (ctx->swrast_context) {
       _tnl_CreateContext(ctx);
@@ -600,11 +575,6 @@ intelInitContext(struct intel_context *intel,
    INTEL_DEBUG = driParseDebugString(getenv("INTEL_DEBUG"), debug_control);
    if (INTEL_DEBUG & DEBUG_BUFMGR)
       dri_bufmgr_set_debug(intel->bufmgr, true);
-   if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && intel->gen < 7) {
-      fprintf(stderr,
-              "shader_time debugging requires gen7 (Ivybridge) or better.\n");
-      INTEL_DEBUG &= ~DEBUG_SHADER_TIME;
-   }
    if (INTEL_DEBUG & DEBUG_PERF)
       intel->perf_debug = true;
 
diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h
index 1c8c87ddb33..036bd79b444 100644
--- a/src/mesa/drivers/dri/i915/intel_context.h
+++ b/src/mesa/drivers/dri/i915/intel_context.h
@@ -216,7 +216,6 @@ struct intel_context
     */
    int gen;
    int gt;
-   bool needs_ff_sync;
    bool is_haswell;
    bool is_baytrail;
    bool is_g4x;
@@ -433,7 +432,6 @@ extern int INTEL_DEBUG;
 #define DEBUG_VS        0x1000000
 #define DEBUG_CLIP      0x2000000
 #define DEBUG_AUB       0x4000000
-#define DEBUG_SHADER_TIME 0x8000000
 #define DEBUG_BLORP     0x10000000
 #define DEBUG_NO16      0x20000000
 
diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
index 6ec432c7e85..85e2705da88 100644
--- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
@@ -147,12 +147,6 @@ intel_miptree_choose_tiling(struct intel_context *intel,
       return I915_TILING_NONE;
    }
 
-   GLenum base_format = _mesa_get_format_base_format(format);
-   if (intel->gen >= 4 &&
-       (base_format == GL_DEPTH_COMPONENT ||
-        base_format == GL_DEPTH_STENCIL_EXT))
-      return I915_TILING_Y;
-
    int minimum_pitch = mt->total_width * mt->cpp;
 
    /* If the width is much smaller than a tile, don't bother tiling. */
@@ -165,11 +159,8 @@ intel_miptree_choose_tiling(struct intel_context *intel,
       return I915_TILING_NONE;
    }
 
-   /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
-   if (intel->gen < 6)
-      return I915_TILING_X;
-
-   return I915_TILING_Y | I915_TILING_X;
+   /* We don't have BLORP to handle Y-tiled blits, so use X-tiling. */
+   return I915_TILING_X;
 }
 
 struct intel_mipmap_tree *
@@ -894,8 +885,7 @@ intel_miptree_map(struct intel_context *intel,
    if (intel->has_llc &&
        !(mode & GL_MAP_WRITE_BIT) &&
        !mt->compressed &&
-       (mt->region->tiling == I915_TILING_X ||
-        (intel->gen >= 6 && mt->region->tiling == I915_TILING_Y)) &&
+       mt->region->tiling == I915_TILING_X &&
        mt->region->pitch < 32768) {
       intel_miptree_map_blit(intel, mt, map, level, slice);
    } else if (mt->region->tiling != I915_TILING_NONE &&
diff --git a/src/mesa/drivers/dri/i915/intel_screen.c b/src/mesa/drivers/dri/i915/intel_screen.c
index 180daee00da..14950e7cfbe 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -159,8 +159,7 @@ intelDRI2Flush(__DRIdrawable *drawable)
    if (intel == NULL)
       return;
 
-   if (intel->gen < 4)
-      INTEL_FIREVERTICES(intel);
+   INTEL_FIREVERTICES(intel);
 
    intel->need_throttle = true;
 
@@ -799,7 +798,6 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
                   const struct gl_config * mesaVis, GLboolean isPixmap)
 {
    struct intel_renderbuffer *rb;
-   struct intel_screen *screen = (struct intel_screen*) driScrnPriv->driverPrivate;
    gl_format rgbFormat;
    struct gl_framebuffer *fb;
 
@@ -818,15 +816,8 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
       rgbFormat = MESA_FORMAT_SARGB8;
    else if (mesaVis->alphaBits == 0)
       rgbFormat = MESA_FORMAT_XRGB8888;
-   else {
-      if (screen->gen >= 4) {
-         rgbFormat = MESA_FORMAT_SARGB8;
-         fb->Visual.sRGBCapable = true;
-      } else {
-         rgbFormat = MESA_FORMAT_ARGB8888;
-      }
-
-   }
+   else
+      rgbFormat = MESA_FORMAT_ARGB8888;
 
    /* setup the hardware-based renderbuffers */
    rb = intel_create_renderbuffer(rgbFormat);
@@ -1004,7 +995,6 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
 
    static const uint8_t singlesample_samples[1] = {0};
 
-   struct intel_screen *screen = dri_screen->driverPrivate;
    uint8_t depth_bits[4], stencil_bits[4];
    __DRIconfig **configs = NULL;
 
@@ -1015,7 +1005,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
 
       /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
        * buffer that has a different number of bits per pixel than the color
-       * buffer, gen >= 6 supports this.
+       * buffer.
        */
       depth_bits[0] = 0;
       stencil_bits[0] = 0;
@@ -1023,11 +1013,6 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
       if (formats[i] == MESA_FORMAT_RGB565) {
          depth_bits[1] = 16;
          stencil_bits[1] = 0;
-         if (screen->gen >= 6) {
-             depth_bits[2] = 24;
-             stencil_bits[2] = 8;
-             num_depth_stencil_bits = 3;
-         }
       } else {
          depth_bits[1] = 24;
          stencil_bits[1] = 8;
@@ -1191,8 +1176,6 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
 				  &has_llc);
    if (success && has_llc)
       intelScreen->hw_has_llc = true;
-   else if (!success && intelScreen->gen >= 6)
-      intelScreen->hw_has_llc = true;
 
    intelScreen->hw_has_swizzling = intel_detect_swizzling(intelScreen);
 
diff --git a/src/mesa/drivers/dri/i915/intel_tex_image.c b/src/mesa/drivers/dri/i915/intel_tex_image.c
index c6f3e903af9..68687df03f7 100644
--- a/src/mesa/drivers/dri/i915/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i915/intel_tex_image.c
@@ -80,8 +80,7 @@ intel_miptree_create_for_teximage(struct intel_context *intel,
        */
       if ((intelObj->base.Sampler.MinFilter == GL_NEAREST ||
 	   intelObj->base.Sampler.MinFilter == GL_LINEAR) &&
-	  intelImage->base.Base.Level == firstLevel &&
-	  (intel->gen < 4 || firstLevel == 0)) {
+	  intelImage->base.Base.Level == firstLevel) {
 	 lastLevel = firstLevel;
       } else {
 	 lastLevel = (firstLevel +
diff --git a/src/mesa/drivers/dri/i915/intel_tex_layout.c b/src/mesa/drivers/dri/i915/intel_tex_layout.c
index eea5441b22b..8a6a44486f2 100644
--- a/src/mesa/drivers/dri/i915/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/intel_tex_layout.c
@@ -74,17 +74,6 @@ intel_horizontal_texture_alignment_unit(struct intel_context *intel,
       return i;
     }
 
-   /* The depth alignment requirements in the table above are for rendering to
-    * depth miplevels using the LOD control fields.  We don't use LOD control
-    * fields, and instead use page offsets plus intra-tile x/y offsets, which
-    * require that the low 3 bits are zero.  To reduce the number of x/y
-    * offset workaround blits we do, align the X to 8, which depth texturing
-    * can handle (sadly, it can't handle 8 in the Y direction).
-    */
-   if (intel->gen >= 7 &&
-       _mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT)
-      return 8;
-
    return 4;
 }
 
@@ -120,14 +109,6 @@ intel_vertical_texture_alignment_unit(struct intel_context *intel,
    if (_mesa_is_format_compressed(format))
       return 4;
 
-   GLenum base_format = _mesa_get_format_base_format(format);
-
-   if (intel->gen >= 6 &&
-       (base_format == GL_DEPTH_COMPONENT ||
-	base_format == GL_DEPTH_STENCIL)) {
-      return 4;
-   }
-
    return 2;
 }
 
diff --git a/src/mesa/drivers/dri/i915/intel_tex_subimage.c b/src/mesa/drivers/dri/i915/intel_tex_subimage.c
index 4f70f883cd8..fd63edf7986 100644
--- a/src/mesa/drivers/dri/i915/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i915/intel_tex_subimage.c
@@ -67,12 +67,6 @@ intel_blit_texsubimage(struct gl_context * ctx,
    if (texImage->TexObject->Target != GL_TEXTURE_2D)
       return false;
 
-   /* On gen6, it's probably not worth swapping to the blit ring to do
-    * this because of all the overhead involved.
-    */
-   if (intel->gen >= 6)
-      return false;
-
    if (!drm_intel_bo_busy(intelImage->mt->region->bo))
       return false;