diff options
| author | Marek Olšák <[email protected]> | 2018-05-02 19:11:37 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-05-10 18:40:01 -0400 |
| commit | 64265ac8d53367c143050df9a8b08b224185e9ae (patch) | |
| tree | 668c6568ba0982b5fc80ad5499b453a1fddbf086 | |
| parent | 14c5a93bfabdc6543b504a0e7ed658e215b4eedb (diff) | |
ac/gpu_info: add kernel_flushes_tc_l2_after_ib
Reviewed-by: Nicolai Hähnle <[email protected]>
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 4 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_gfx_cs.c | 3 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1 |
4 files changed, 7 insertions, 2 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 1c7abdb87cb..4eeb6042eef 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -324,6 +324,9 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->has_gpu_reset_counter_query = false; info->has_eqaa_surface_allocator = true; info->has_format_bc1_through_bc7 = true; + /* DRM 3.1.0 doesn't flush TC for VI correctly. */ + info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI || + info->drm_minor >= 2; info->num_render_backends = amdinfo->rb_pipes; /* The value returned by the kernel driver was wrong. */ @@ -479,6 +482,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query); printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator); printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7); + printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 9c4c6cb11f0..5e404714db6 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -104,6 +104,7 @@ struct radeon_info { bool has_gpu_reset_counter_query; bool has_eqaa_surface_allocator; bool has_format_bc1_through_bc7; + bool kernel_flushes_tc_l2_after_ib; /* Shader cores. */ uint32_t r600_max_quad_pipes; /* wave size / 16 */ diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index 0af16dd3474..ec74c1bc703 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -74,8 +74,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, if (ctx->gfx_flush_in_progress) return; - if (ctx->chip_class == VI && ctx->screen->info.drm_minor <= 1) { - /* DRM 3.1.0 doesn't flush TC for VI correctly. */ + if (!ctx->screen->info.kernel_flushes_tc_l2_after_ib) { wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_INV_GLOBAL_L2; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 108c1af9985..1b029e94969 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -538,6 +538,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43; ws->info.has_eqaa_surface_allocator = false; ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31; + ws->info.kernel_flushes_tc_l2_after_ib = true; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; |