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authorLuca Barbieri <[email protected]>2010-09-04 02:26:37 +0200
committerLuca Barbieri <[email protected]>2010-09-04 02:27:59 +0200
commit351a669465e2fc8c3108f0eab751f24bc0976264 (patch)
tree86a713e3d2c0c4f933fb8781bfd564c8ebbf1071
parentfa82ad84fbe2be2bbfe9de7cda3e901a069ae16c (diff)
nvfx: support all possible vs consts
We were incorrectly setting a register that limited the range of constants accessible via indirect addressing. Setting it correctly, we can address all the constants the GPU supports.
-rw-r--r--src/gallium/drivers/nvfx/nvfx_screen.c15
1 files changed, 5 insertions, 10 deletions
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
index b5b7a340819..335c500355e 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ b/src/gallium/drivers/nvfx/nvfx_screen.c
@@ -110,8 +110,9 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_VS_INPUTS:
return 16;
case PIPE_CAP_MAX_VS_CONSTS:
- /* XXX: currently more don't work, but it should be possible to make it work */
- return 212 - 6;
+ /* - 6 is for clip planes; Gallium should be fixed to put
+ * them in the vertex shader itself, so we don't need to reserve these */
+ return (screen->is_nv4x ? 468 : 256) - 6;
case PIPE_CAP_MAX_VS_TEMPS:
return screen->is_nv4x ? 32 : 13;
case PIPE_CAP_MAX_VS_ADDRS:
@@ -325,7 +326,7 @@ static void nv40_screen_init(struct nvfx_screen *screen)
OUT_RING(chan, RING_3D(0x1ef8, 1));
OUT_RING(chan, 0x0020ffff);
OUT_RING(chan, RING_3D(0x1d64, 1));
- OUT_RING(chan, 0x00d30000);
+ OUT_RING(chan, 0x01d300d4);
OUT_RING(chan, RING_3D(0x1e94, 1));
OUT_RING(chan, 0x00000001);
@@ -478,13 +479,7 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
/* Vtxprog resources */
if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) ||
- /* XXX: this should actually be 468 or 256, but apparently indirect addressing
- * cannot read consts starting from 212 on nv40.
- * It looks like 44 slots are reserved for something, and there is a "mode switch"
- * from 256 slots to 512 slots that we are setting to "256 mode" on nv40, leading
- * to 212 = 256 - 44 instead of 468 = 512 - 44 usable slots.
- */
- nouveau_resource_init(&screen->vp_data_heap, 0, 212)) {
+ nouveau_resource_init(&screen->vp_data_heap, 0, screen->is_nv4x ? 468 : 256)) {
nvfx_screen_destroy(pscreen);
return NULL;
}