diff options
| author | Anuj Phogat <[email protected]> | 2018-05-31 16:03:44 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-07-09 15:38:42 -0700 |
| commit | 2badf0e85b3a54119b08c559dc18aed43a156295 (patch) | |
| tree | 9226ec23b0f30aa7c067431678ee3ad914a4f881 | |
| parent | c1d8300117891ec87762caa30d14307622c65bcf (diff) | |
i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS
CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index d8273aa5734..757426407c3 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -64,10 +64,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_upload_invariant_state(brw); if (devinfo->gen == 10 || devinfo->gen == 11) { - brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS, - REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) | - GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE); - /* From gen10 workaround table in h/w specs: * * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1 |