diff options
| author | Jason Ekstrand <[email protected]> | 2017-09-06 20:32:30 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2017-11-07 10:37:52 -0800 |
| commit | 1f416630079f38110910ba796f70e2b81e9ddbf4 (patch) | |
| tree | c6750559fe25bf1196e56114786f3305e6f3db96 | |
| parent | 6c00240bc650805e0b66aa6e17dbe69bbe41e446 (diff) | |
intel/fs: Use an explicit D type for vote any/all/eq intrinsics
The any/all intrinsics return a boolean value so D or UD is the correct
type. Unfortunately, get_nir_dest has the annoying behavior of
returnning a float type by default. This causes format conversion which
gives us -1.0f or 0.0f in the register. If the consumer of the result
does an integer comparison to zero, it will give you the right boolean
value but if we do something more clever based on the 0/~0 assumption
for booleans, this will give the wrong value.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index dcd9942f369..3143bc6eea1 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4207,6 +4207,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0)); } bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ); + + dest.type = BRW_REGISTER_TYPE_D; bld.MOV(dest, brw_imm_d(-1)); set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ANY8H : dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ANY16H : @@ -4229,6 +4231,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff)); } bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ); + + dest.type = BRW_REGISTER_TYPE_D; bld.MOV(dest, brw_imm_d(-1)); set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ALL8H : dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H : @@ -4253,6 +4257,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff)); } bld.CMP(bld.null_reg_d(), value, uniformized, BRW_CONDITIONAL_Z); + + dest.type = BRW_REGISTER_TYPE_D; bld.MOV(dest, brw_imm_d(-1)); set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ALL8H : dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H : |