diff options
author | Anuj Phogat <[email protected]> | 2015-04-14 22:06:47 -0700 |
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committer | Anuj Phogat <[email protected]> | 2015-06-08 13:57:11 -0700 |
commit | 126078faca7a9da0f825d3ad07ce9b1183737240 (patch) | |
tree | 2a6a7fb40240388ae0950f97c7bfe22cde44ea2f | |
parent | ef6b9985ea6b60a562daed3a9ed3be0f91f21e01 (diff) |
i965/gen9: Set tiled resource mode for the miptree
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_tex_layout.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index ec7c6c4daa0..e461bfc4e05 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -568,6 +568,8 @@ brw_miptree_layout(struct brw_context *brw, { bool gen6_hiz_or_stencil = false; + mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE; + if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) { const GLenum base_format = _mesa_get_format_base_format(mt->format); gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 0db6b44b9fd..20bed5378ca 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -330,6 +330,13 @@ struct intel_miptree_aux_buffer struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */ }; +/* Tile resource modes */ +enum intel_miptree_tr_mode { + INTEL_MIPTREE_TRMODE_NONE, + INTEL_MIPTREE_TRMODE_YF, + INTEL_MIPTREE_TRMODE_YS +}; + struct intel_mipmap_tree { /** Buffer object containing the pixel data. */ @@ -338,6 +345,7 @@ struct intel_mipmap_tree uint32_t pitch; /**< pitch in bytes. */ uint32_t tiling; /**< One of the I915_TILING_* flags */ + enum intel_miptree_tr_mode tr_mode; /* Effectively the key: */ |