diff options
| author | Marek Olšák <[email protected]> | 2017-08-27 22:27:01 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-08-27 22:27:23 +0200 |
| commit | d500c9b060e1715e8d3a984d4a5c6f6179f46943 (patch) | |
| tree | 1aace0cad1ab7bebe03939e4bb18d60a97da140e | |
| parent | 9573bd70e1e7e32527d9c40716174c30fcc9720e (diff) | |
Revert "radeonsi: get the raster config from AMDGPU on SI"
This reverts commit fc99cb3c9edee3af773700cf7ebdc60dc02fcaba.
"The performance went down from 64.7 to 51.4 fps in Valley and from 30.8 to
25.1 fps in Heaven on Radeon HD 7970. Other games seem to have also a 10-25%
performance decrease."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102429
It looks like we can't use the raster config values from the kernel.
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 3 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 17 |
3 files changed, 0 insertions, 22 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 84a54bb094f..e55d864187d 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -301,9 +301,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode, sizeof(amdinfo->gb_tile_mode)); info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask; - memcpy(info->pa_sc_raster_config, amdinfo->pa_sc_raster_cfg, - sizeof(info->pa_sc_raster_config)); - info->pa_sc_raster_config_1 = amdinfo->pa_sc_raster_cfg1[0]; memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode, sizeof(amdinfo->gb_macro_tile_mode)); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 91d303aee40..06b0c775466 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -96,8 +96,6 @@ struct radeon_info { uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ uint32_t pipe_interleave_bytes; uint32_t enabled_rb_mask; /* GCN harvest config */ - uint32_t pa_sc_raster_config[4]; /* per SE */ - uint32_t pa_sc_raster_config_1; uint64_t max_alignment; /* from addrlib */ /* Tile modes. */ diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 24e509cda8b..4772df25d1f 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4421,23 +4421,6 @@ si_write_harvested_raster_configs(struct si_context *sctx, static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4) { struct si_screen *sscreen = sctx->screen; - - /* On SI, set the raster config value from AMDGPU. */ - if (sscreen->b.info.drm_major == 3 && sscreen->b.chip_class == SI) { - if (sscreen->b.info.max_se == 1) { - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, - sscreen->b.info.pa_sc_raster_config[0]); - } else { - for (unsigned se = 0; se < sscreen->b.info.max_se; se++) { - si_set_grbm_gfx_index_se(sctx, pm4, se); - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, - sscreen->b.info.pa_sc_raster_config[se]); - } - si_set_grbm_gfx_index_se(sctx, pm4, ~0); - } - return; - } - unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16); unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask; unsigned raster_config, raster_config_1; |