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authorIan Romanick <[email protected]>2018-08-24 17:24:36 -0700
committerIan Romanick <[email protected]>2018-08-28 15:35:50 -0700
commitc836326a290e867e736478b340fca725a978309f (patch)
tree785a88f65f99ceb945993ab06299dceedf21bb62
parentc856403868e6bd34a19131189333cefd67a374ce (diff)
i965/vec4: Emit BRW_AOP_INC or BRW_AOP_DEC for atomicAdd of +1 or -1
No shader-db changes on any Intel platform. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
-rw-r--r--src/intel/compiler/brw_vec4_nir.cpp19
1 files changed, 16 insertions, 3 deletions
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index 4c3a2d2e10a..124714b59de 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -709,9 +709,20 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
break;
}
- case nir_intrinsic_ssbo_atomic_add:
- nir_emit_ssbo_atomic(BRW_AOP_ADD, instr);
+ case nir_intrinsic_ssbo_atomic_add: {
+ int op = BRW_AOP_ADD;
+ const nir_const_value *const val = nir_src_as_const_value(instr->src[2]);
+
+ if (val != NULL) {
+ if (val->i32[0] == 1)
+ op = BRW_AOP_INC;
+ else if (val->i32[0] == -1)
+ op = BRW_AOP_DEC;
+ }
+
+ nir_emit_ssbo_atomic(op, instr);
break;
+ }
case nir_intrinsic_ssbo_atomic_imin:
nir_emit_ssbo_atomic(BRW_AOP_IMIN, instr);
break;
@@ -937,7 +948,9 @@ vec4_visitor::nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr)
}
src_reg offset = get_nir_src(instr->src[1], 1);
- src_reg data1 = get_nir_src(instr->src[2], 1);
+ src_reg data1;
+ if (op != BRW_AOP_INC && op != BRW_AOP_DEC && op != BRW_AOP_PREDEC)
+ data1 = get_nir_src(instr->src[2], 1);
src_reg data2;
if (op == BRW_AOP_CMPWR)
data2 = get_nir_src(instr->src[3], 1);