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authorRob Clark <[email protected]>2015-07-25 12:48:18 -0400
committerRob Clark <[email protected]>2015-07-27 13:51:06 -0400
commita240748de52f2e469e91b60d29ae872828a594d7 (patch)
tree7bf41ab38a49865432109005444b959aaa294ea9
parentbe8a8ebe578267ab24e343c3c1347936a221468e (diff)
freedreno/ir3: cleanup driver-param stuff
Add 'enum ir3_driver_param' to track driver-param slots, and a create_driver_param() helper to avoid having the knowledge about where driver params are placed in const regs spread throughout the code as we add additional driver-params. Signed-off-by: Rob Clark <[email protected]>
-rw-r--r--src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c31
-rw-r--r--src/gallium/drivers/freedreno/ir3/ir3_shader.c5
-rw-r--r--src/gallium/drivers/freedreno/ir3/ir3_shader.h5
3 files changed, 31 insertions, 10 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index bdbaf8970cf..e013abedce6 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -261,13 +261,26 @@ compile_init(struct ir3_compiler *compiler,
so->first_driver_param = so->first_immediate = ctx->s->num_uniforms;
- /* one (vec4) slot for vertex id base: */
- if (so->type == SHADER_VERTEX)
- so->first_immediate++;
+ /* Layout of constant registers:
+ *
+ * num_uniform * vec4 - user consts
+ * 4 * vec4 - UBO addresses
+ * if (vertex shader) {
+ * 1 * vec4 - driver params (IR3_DP_*)
+ * }
+ *
+ * TODO this could be made more dynamic, to at least skip sections
+ * that we don't need..
+ */
/* reserve 4 (vec4) slots for ubo base addresses: */
so->first_immediate += 4;
+ if (so->type == SHADER_VERTEX) {
+ /* one (vec4) slot for driver params (see ir3_driver_param): */
+ so->first_immediate++;
+ }
+
return ctx;
}
@@ -811,6 +824,14 @@ create_frag_face(struct ir3_compile *ctx, unsigned comp)
}
}
+static struct ir3_instruction *
+create_driver_param(struct ir3_compile *ctx, enum ir3_driver_param dp)
+{
+ /* first four vec4 sysval's reserved for UBOs: */
+ unsigned r = regid(ctx->so->first_driver_param + 4, dp);
+ return create_uniform(ctx, r);
+}
+
/* helper for instructions that produce multiple consecutive scalar
* outputs which need to have a split/fanout meta instruction inserted
*/
@@ -1415,9 +1436,7 @@ emit_intrinisic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
break;
case nir_intrinsic_load_base_vertex:
if (!ctx->basevertex) {
- /* first four vec4 sysval's reserved for UBOs: */
- unsigned r = regid(ctx->so->first_driver_param + 4, 0);
- ctx->basevertex = create_uniform(ctx, r);
+ ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
add_sysval_input(ctx, TGSI_SEMANTIC_BASEVERTEX,
ctx->basevertex);
}
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
index 75425e91378..166eb007dbb 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
@@ -548,10 +548,7 @@ ir3_emit_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
uint32_t offset = v->first_driver_param + 4; /* driver params after UBOs */
if (v->constlen >= offset) {
uint32_t vertex_params[4] = {
- info->indexed ? info->index_bias : info->start,
- 0,
- 0,
- 0
+ [IR3_DP_VTXID_BASE] = info->indexed ? info->index_bias : info->start,
};
fd_wfi(ctx, ring);
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index f0af4478109..4cb25205324 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -34,6 +34,11 @@
#include "ir3.h"
#include "disasm.h"
+/* driver param indices: */
+enum ir3_driver_param {
+ IR3_DP_VTXID_BASE = 0,
+};
+
/* internal semantic used for passing vtxcnt to vertex shader to
* implement transform feedback:
*/