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authorJonathan Marek <[email protected]>2019-02-19 22:41:54 +0100
committerRob Clark <[email protected]>2019-02-27 18:46:28 +0000
commit8eca6df5ed5ad6df51a3aad271856d7da56d1292 (patch)
treec3f0f19abbdda9ee95b362fc7047de36f142357e
parent357313ab0f123b4e4b1efc74f5e5b1514c421e68 (diff)
freedreno: a2xx: add use_hw_binning function
Fixes: cb2322c7 Signed-off-by: Jonathan Marek <[email protected]>
-rw-r--r--src/gallium/drivers/freedreno/a2xx/fd2_gmem.c26
1 files changed, 24 insertions, 2 deletions
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
index 41636c29648..84483bc2fc7 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
@@ -59,6 +59,28 @@ static uint32_t fmt2swap(enum pipe_format format)
}
}
+static bool
+use_hw_binning(struct fd_batch *batch)
+{
+ struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+
+ /* we hardcoded a limit of 8 "pipes", we can increase this limit
+ * at the cost of a slightly larger command stream
+ * however very few cases will need more than 8
+ * gmem->num_vsc_pipes == 0 means empty batch (TODO: does it still happen?)
+ */
+ if (gmem->num_vsc_pipes > 8 || !gmem->num_vsc_pipes)
+ return false;
+
+ /* only a20x hw binning is implement
+ * a22x is more like a3xx, but perhaps the a20x works? (TODO)
+ */
+ if (!is_a20x(batch->ctx->screen))
+ return false;
+
+ return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
+}
+
/* transfer from gmem to system memory (ie. normal RAM) */
static void
@@ -533,7 +555,7 @@ fd2_emit_tile_init(struct fd_batch *batch)
OUT_RING(ring, CP_REG(REG_A2XX_VGT_CURRENT_BIN_ID_MAX));
OUT_RING(ring, 0);
- if (is_a20x(ctx->screen) && fd_binning_enabled && gmem->num_vsc_pipes) {
+ if (use_hw_binning(batch)) {
/* patch out unneeded memory exports by changing EXEC CF to EXEC_END
*
* in the shader compiler, we guarantee that the shader ends with
@@ -692,7 +714,7 @@ fd2_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
OUT_RING(ring, fui(0.0f));
}
- if (is_a20x(ctx->screen) && fd_binning_enabled) {
+ if (use_hw_binning(batch)) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
OUT_PKT3(ring, CP_SET_CONSTANT, 2);