diff options
| author | Anuj Phogat <[email protected]> | 2019-01-24 14:46:02 -0800 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2019-03-19 14:42:19 -0700 |
| commit | 2be60e0c73ed1555a919c5725cc0cab119a2b6de (patch) | |
| tree | d983e195a83f07a0dd4c5338d8662bc5d0dea4e5 | |
| parent | 85ecd14ef6a084f5e82860de6dbc79870b335682 (diff) | |
anv/icl: Add WA_2204188704 to disable pixel shader panic dispatch
Signed-off-by: Anuj Phogat <[email protected]>
Acked-by: Jason Ekstrand <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
| -rw-r--r-- | src/intel/genxml/gen11.xml | 5 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_state.c | 12 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index a7c06c5ab60..6f3aba46561 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -3681,4 +3681,9 @@ <field name="Enabled Texel Offset Precision Fix Mask" start="17" end="17" type="bool"/> </register> + <register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304"> + <field name="PS Thread Panic Dispatch" start="6" end="7" type="uint"/> + <field name="PS Thread Panic Dispatch Mask" start="22" end="23" type="uint"/> + </register> + </genxml> diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index cffd1e47247..6d55e5dc5c6 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -200,6 +200,18 @@ genX(init_device_state)(struct anv_device *device) lri.DataDWord = half_slice_chicken7; } + /* WA_2204188704: Pixel Shader Panic dispatch must be disabled. + */ + uint32_t common_slice_chicken3; + anv_pack_struct(&common_slice_chicken3, GENX(COMMON_SLICE_CHICKEN3), + .PSThreadPanicDispatch = 0x3, + .PSThreadPanicDispatchMask = 0x3); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(COMMON_SLICE_CHICKEN3_num); + lri.DataDWord = common_slice_chicken3; + } + #endif /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so |