diff options
author | Anuj Phogat <[email protected]> | 2018-10-24 11:35:42 -0700 |
---|---|---|
committer | Anuj Phogat <[email protected]> | 2018-11-02 08:34:33 -0700 |
commit | 1c140470effe844889d4d099f6b40fedfe503b06 (patch) | |
tree | a0a0609cee9aa6cdf3a060091155a4dafdf7863b | |
parent | 9a41a10f8aa0d93adefc14ad1b7235a6b7b35d4f (diff) |
anv/icl: Disable prefetching of sampler state entries
WA_1606682166:
Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
Disable the Sampler state prefetch functionality in the SARB by
programming 0xB000[30] to '1'. This is to be done at boot time and
the feature must remain disabled permanently.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
-rw-r--r-- | src/intel/vulkan/genX_pipeline.c | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index cc485541763..cf15e79db51 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1198,7 +1198,12 @@ emit_3dstate_vs(struct anv_pipeline *pipeline) vs.SingleVertexDispatch = false; #endif vs.VectorMaskEnable = false; - vs.SamplerCount = get_sampler_count(vs_bin); + /* WA_1606682166: + * Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes. + * Disable the Sampler state prefetch functionality in the SARB by + * programming 0xB000[30] to '1'. + */ + vs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(vs_bin); /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to * disable prefetching of binding tables on A0 and B0 steppings. * TODO: Revisit this WA on newer steppings. @@ -1273,8 +1278,8 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline, hs.Enable = true; hs.StatisticsEnable = true; hs.KernelStartPointer = tcs_bin->kernel.offset; - - hs.SamplerCount = get_sampler_count(tcs_bin); + /* WA_1606682166 */ + hs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(tcs_bin); /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */ hs.BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(tcs_bin); hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1; @@ -1324,8 +1329,8 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline, ds.Enable = true; ds.StatisticsEnable = true; ds.KernelStartPointer = tes_bin->kernel.offset; - - ds.SamplerCount = get_sampler_count(tes_bin); + /* WA_1606682166 */ + ds.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(tes_bin); /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */ ds.BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(tes_bin); ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1; @@ -1383,7 +1388,8 @@ emit_3dstate_gs(struct anv_pipeline *pipeline) gs.SingleProgramFlow = false; gs.VectorMaskEnable = false; - gs.SamplerCount = get_sampler_count(gs_bin); + /* WA_1606682166 */ + gs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(gs_bin); /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */ gs.BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(gs_bin); gs.IncludeVertexHandles = gs_prog_data->base.include_vue_handles; @@ -1616,7 +1622,8 @@ emit_3dstate_ps(struct anv_pipeline *pipeline, ps.SingleProgramFlow = false; ps.VectorMaskEnable = true; - ps.SamplerCount = get_sampler_count(fs_bin); + /* WA_1606682166 */ + ps.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(fs_bin); /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */ ps.BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(fs_bin); ps.PushConstantEnable = wm_prog_data->base.nr_params > 0 || @@ -1947,8 +1954,8 @@ compute_pipeline_create( struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = { .KernelStartPointer = cs_bin->kernel.offset, - - .SamplerCount = get_sampler_count(cs_bin), + /* WA_1606682166 */ + .SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(cs_bin), /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */ .BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(cs_bin), .BarrierEnable = cs_prog_data->uses_barrier, |