diff options
| author | Chia-I Wu <[email protected]> | 2014-04-13 00:33:00 +0800 |
|---|---|---|
| committer | Chia-I Wu <[email protected]> | 2014-04-14 20:45:03 +0800 |
| commit | 01e3e82a56310932667c60bcca9cc9fdfd8b87c4 (patch) | |
| tree | d298945bbcdd31cae3df0f0b66af715c63f03e05 | |
| parent | d75a8799fded5f8cd7ae4b20d935ff8a088dc122 (diff) | |
ilo: add genhw headers
All except genhw.h are generated by https://github.com/olvaffe/envytools/.
intel_chipset.h is deprecated.
22 files changed, 3504 insertions, 131 deletions
diff --git a/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h b/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h new file mode 100644 index 00000000000..07e64758aff --- /dev/null +++ b/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h @@ -0,0 +1,116 @@ +#ifndef GEN_BLITTER_XML +#define GEN_BLITTER_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +https://github.com/olvaffe/envytools/ +git clone https://github.com/olvaffe/envytools.git + +Copyright (C) 2014 by the following authors: +- Chia-I Wu <[email protected]> (olv) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define GEN6_BLITTER_TYPE__MASK 0xe0000000 +#define GEN6_BLITTER_TYPE__SHIFT 29 +#define GEN6_BLITTER_TYPE_BLITTER (0x2 << 29) +#define GEN6_BLITTER_OPCODE__MASK 0x1fc00000 +#define GEN6_BLITTER_OPCODE__SHIFT 22 +#define GEN6_BLITTER_OPCODE_COLOR_BLT (0x40 << 22) +#define GEN6_BLITTER_OPCODE_SRC_COPY_BLT (0x43 << 22) +#define GEN6_BLITTER_OPCODE_XY_COLOR_BLT (0x50 << 22) +#define GEN6_BLITTER_OPCODE_XY_SRC_COPY_BLT (0x53 << 22) +#define GEN6_BLITTER_BR00_WRITE_A (0x1 << 21) +#define GEN6_BLITTER_BR00_WRITE_RGB (0x1 << 20) +#define GEN6_BLITTER_BR00_SRC_TILED (0x1 << 15) +#define GEN6_BLITTER_BR00_DST_TILED (0x1 << 11) +#define GEN6_BLITTER_LENGTH__MASK 0x0000003f +#define GEN6_BLITTER_LENGTH__SHIFT 0 +#define GEN6_BLITTER_BR13_CLIP_ENABLE (0x1 << 30) +#define GEN6_BLITTER_BR13_DIR_RTL (0x1 << 30) +#define GEN6_BLITTER_BR13_FORMAT__MASK 0x03000000 +#define GEN6_BLITTER_BR13_FORMAT__SHIFT 24 +#define GEN6_BLITTER_BR13_FORMAT_8 (0x0 << 24) +#define GEN6_BLITTER_BR13_FORMAT_565 (0x1 << 24) +#define GEN6_BLITTER_BR13_FORMAT_1555 (0x2 << 24) +#define GEN6_BLITTER_BR13_FORMAT_8888 (0x3 << 24) +#define GEN6_BLITTER_BR13_ROP__MASK 0x00ff0000 +#define GEN6_BLITTER_BR13_ROP__SHIFT 16 +#define GEN6_BLITTER_BR13_ROP_SRCCOPY (0xcc << 16) +#define GEN6_BLITTER_BR13_ROP_PATCOPY (0xf0 << 16) +#define GEN6_BLITTER_BR13_DST_PITCH__MASK 0x0000ffff +#define GEN6_BLITTER_BR13_DST_PITCH__SHIFT 0 +#define GEN6_BLITTER_BR11_SRC_PITCH__MASK 0x0000ffff +#define GEN6_BLITTER_BR11_SRC_PITCH__SHIFT 0 +#define GEN6_BLITTER_BR14_DST_HEIGHT__MASK 0xffff0000 +#define GEN6_BLITTER_BR14_DST_HEIGHT__SHIFT 16 +#define GEN6_BLITTER_BR14_DST_WIDTH__MASK 0x0000ffff +#define GEN6_BLITTER_BR14_DST_WIDTH__SHIFT 0 +#define GEN6_BLITTER_BR22_DST_Y1__MASK 0xffff0000 +#define GEN6_BLITTER_BR22_DST_Y1__SHIFT 16 +#define GEN6_BLITTER_BR22_DST_X1__MASK 0x0000ffff +#define GEN6_BLITTER_BR22_DST_X1__SHIFT 0 +#define GEN6_BLITTER_BR23_DST_Y2__MASK 0xffff0000 +#define GEN6_BLITTER_BR23_DST_Y2__SHIFT 16 +#define GEN6_BLITTER_BR23_DST_X2__MASK 0x0000ffff +#define GEN6_BLITTER_BR23_DST_X2__SHIFT 0 +#define GEN6_BLITTER_BR26_SRC_Y1__MASK 0xffff0000 +#define GEN6_BLITTER_BR26_SRC_Y1__SHIFT 16 +#define GEN6_BLITTER_BR26_SRC_X1__MASK 0x0000ffff +#define GEN6_BLITTER_BR26_SRC_X1__SHIFT 0 +#define GEN6_COLOR_BLT__SIZE 5 + + + + + + +#define GEN6_SRC_COPY_BLT__SIZE 6 + + + + + + + +#define GEN6_XY_COLOR_BLT__SIZE 6 + + + + + + + +#define GEN6_XY_SRC_COPY_BLT__SIZE 8 + + + + + + + + + + +#endif /* GEN_BLITTER_XML */ diff --git a/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h b/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h new file mode 100644 index 00000000000..e8b85977898 --- /dev/null +++ b/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h @@ -0,0 +1,461 @@ +#ifndef GEN_EU_ISA_XML +#define GEN_EU_ISA_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +https://github.com/olvaffe/envytools/ +git clone https://github.com/olvaffe/envytools.git + +Copyright (C) 2014 by the following authors: +- Chia-I Wu <[email protected]> (olv) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define GEN6_OPCODE_ILLEGAL 0x0 +#define GEN6_OPCODE_MOV 0x1 +#define GEN6_OPCODE_SEL 0x2 +#define GEN6_OPCODE_MOVI 0x3 +#define GEN6_OPCODE_NOT 0x4 +#define GEN6_OPCODE_AND 0x5 +#define GEN6_OPCODE_OR 0x6 +#define GEN6_OPCODE_XOR 0x7 +#define GEN6_OPCODE_SHR 0x8 +#define GEN6_OPCODE_SHL 0x9 +#define GEN6_OPCODE_DIM 0xa +#define GEN6_OPCODE_ASR 0xc +#define GEN6_OPCODE_CMP 0x10 +#define GEN6_OPCODE_CMPN 0x11 +#define GEN7_OPCODE_CSEL 0x12 +#define GEN7_OPCODE_F32TO16 0x13 +#define GEN7_OPCODE_F16TO32 0x14 +#define GEN7_OPCODE_BFREV 0x17 +#define GEN7_OPCODE_BFE 0x18 +#define GEN7_OPCODE_BFI1 0x19 +#define GEN7_OPCODE_BFI2 0x1a +#define GEN6_OPCODE_JMPI 0x20 +#define GEN7_OPCODE_BRD 0x21 +#define GEN6_OPCODE_IF 0x22 +#define GEN7_OPCODE_BRC 0x23 +#define GEN6_OPCODE_ELSE 0x24 +#define GEN6_OPCODE_ENDIF 0x25 +#define GEN6_OPCODE_CASE 0x26 +#define GEN6_OPCODE_WHILE 0x27 +#define GEN6_OPCODE_BREAK 0x28 +#define GEN6_OPCODE_CONT 0x29 +#define GEN6_OPCODE_HALT 0x2a +#define GEN75_OPCODE_CALLA 0x2b +#define GEN6_OPCODE_CALL 0x2c +#define GEN6_OPCODE_RETURN 0x2d +#define GEN6_OPCODE_WAIT 0x30 +#define GEN6_OPCODE_SEND 0x31 +#define GEN6_OPCODE_SENDC 0x32 +#define GEN6_OPCODE_MATH 0x38 +#define GEN6_OPCODE_ADD 0x40 +#define GEN6_OPCODE_MUL 0x41 +#define GEN6_OPCODE_AVG 0x42 +#define GEN6_OPCODE_FRC 0x43 +#define GEN6_OPCODE_RNDU 0x44 +#define GEN6_OPCODE_RNDD 0x45 +#define GEN6_OPCODE_RNDE 0x46 +#define GEN6_OPCODE_RNDZ 0x47 +#define GEN6_OPCODE_MAC 0x48 +#define GEN6_OPCODE_MACH 0x49 +#define GEN6_OPCODE_LZD 0x4a +#define GEN7_OPCODE_FBH 0x4b +#define GEN7_OPCODE_FBL 0x4c +#define GEN7_OPCODE_CBIT 0x4d +#define GEN7_OPCODE_ADDC 0x4e +#define GEN7_OPCODE_SUBB 0x4f +#define GEN6_OPCODE_SAD2 0x50 +#define GEN6_OPCODE_SADA2 0x51 +#define GEN6_OPCODE_DP4 0x54 +#define GEN6_OPCODE_DPH 0x55 +#define GEN6_OPCODE_DP3 0x56 +#define GEN6_OPCODE_DP2 0x57 +#define GEN6_OPCODE_LINE 0x59 +#define GEN6_OPCODE_PLN 0x5a +#define GEN6_OPCODE_MAD 0x5b +#define GEN6_OPCODE_LRP 0x5c +#define GEN6_OPCODE_NOP 0x7e +#define GEN6_ALIGN_1 0x0 +#define GEN6_ALIGN_16 0x1 +#define GEN6_MASKCTRL_NORMAL 0x0 +#define GEN6_MASKCTRL_NOMASK 0x1 +#define GEN6_DEPCTRL_NORMAL 0x0 +#define GEN6_DEPCTRL_NODDCLR 0x1 +#define GEN6_DEPCTRL_NODDCHK 0x2 +#define GEN6_DEPCTRL_NEITHER 0x3 +#define GEN6_QTRCTRL_1Q 0x0 +#define GEN6_QTRCTRL_2Q 0x1 +#define GEN6_QTRCTRL_3Q 0x2 +#define GEN6_QTRCTRL_4Q 0x3 +#define GEN6_QTRCTRL_1H 0x0 +#define GEN6_QTRCTRL_2H 0x2 +#define GEN6_THREADCTRL_NORMAL 0x0 +#define GEN6_THREADCTRL_ATOMIC 0x1 +#define GEN6_THREADCTRL_SWITCH 0x2 +#define GEN6_PREDCTRL_NONE 0x0 +#define GEN6_PREDCTRL_NORMAL 0x1 +#define GEN6_PREDCTRL_ANYV 0x2 +#define GEN6_PREDCTRL_ALLV 0x3 +#define GEN6_PREDCTRL_ANY2H 0x4 +#define GEN6_PREDCTRL_ALL2H 0x5 +#define GEN6_PREDCTRL_X 0x2 +#define GEN6_PREDCTRL_Y 0x3 +#define GEN6_PREDCTRL_Z 0x4 +#define GEN6_PREDCTRL_W 0x5 +#define GEN6_PREDCTRL_ANY4H 0x6 +#define GEN6_PREDCTRL_ALL4H 0x7 +#define GEN6_PREDCTRL_ANY8H 0x8 +#define GEN6_PREDCTRL_ALL8H 0x9 +#define GEN6_PREDCTRL_ANY16H 0xa +#define GEN6_PREDCTRL_ALL16H 0xb +#define GEN7_PREDCTRL_ANY32H 0xc +#define GEN7_PREDCTRL_ALL32H 0xd +#define GEN6_EXECSIZE_1 0x0 +#define GEN6_EXECSIZE_2 0x1 +#define GEN6_EXECSIZE_4 0x2 +#define GEN6_EXECSIZE_8 0x3 +#define GEN6_EXECSIZE_16 0x4 +#define GEN6_EXECSIZE_32 0x5 +#define GEN6_COND_NORMAL 0x0 +#define GEN6_COND_Z 0x1 +#define GEN6_COND_NZ 0x2 +#define GEN6_COND_G 0x3 +#define GEN6_COND_GE 0x4 +#define GEN6_COND_L 0x5 +#define GEN6_COND_LE 0x6 +#define GEN6_COND_O 0x8 +#define GEN6_COND_U 0x9 +#define GEN6_MATH_INV 0x1 +#define GEN6_MATH_LOG 0x2 +#define GEN6_MATH_EXP 0x3 +#define GEN6_MATH_SQRT 0x4 +#define GEN6_MATH_RSQ 0x5 +#define GEN6_MATH_SIN 0x6 +#define GEN6_MATH_COS 0x7 +#define GEN6_MATH_FDIV 0x9 +#define GEN6_MATH_POW 0xa +#define GEN6_MATH_INT_DIV 0xb +#define GEN6_MATH_INT_DIV_QUOTIENT 0xc +#define GEN6_MATH_INT_DIV_REMAINDER 0xd +#define GEN6_SFID_NULL 0x0 +#define GEN6_SFID_SAMPLER 0x2 +#define GEN6_SFID_GATEWAY 0x3 +#define GEN6_SFID_DP_SAMPLER 0x4 +#define GEN6_SFID_DP_RC 0x5 +#define GEN6_SFID_URB 0x6 +#define GEN6_SFID_SPAWNER 0x7 +#define GEN6_SFID_VME 0x8 +#define GEN6_SFID_DP_CC 0x9 +#define GEN7_SFID_DP_DC0 0xa +#define GEN7_SFID_PI 0xb +#define GEN75_SFID_DP_DC1 0xc +#define GEN6_FILE_ARF 0x0 +#define GEN6_FILE_GRF 0x1 +#define GEN6_FILE_MRF 0x2 +#define GEN6_FILE_IMM 0x3 +#define GEN6_TYPE_UD 0x0 +#define GEN6_TYPE_D 0x1 +#define GEN6_TYPE_UW 0x2 +#define GEN6_TYPE_W 0x3 +#define GEN6_TYPE_UB 0x4 +#define GEN6_TYPE_B 0x5 +#define GEN7_TYPE_DF 0x6 +#define GEN6_TYPE_F 0x7 +#define GEN6_TYPE_UV_IMM 0x4 +#define GEN6_TYPE_VF_IMM 0x5 +#define GEN6_TYPE_V_IMM 0x6 +#define GEN7_TYPE_F_3SRC 0x0 +#define GEN7_TYPE_D_3SRC 0x1 +#define GEN7_TYPE_UD_3SRC 0x2 +#define GEN7_TYPE_DF_3SRC 0x3 +#define GEN6_VERTSTRIDE_0 0x0 +#define GEN6_VERTSTRIDE_1 0x1 +#define GEN6_VERTSTRIDE_2 0x2 +#define GEN6_VERTSTRIDE_4 0x3 +#define GEN6_VERTSTRIDE_8 0x4 +#define GEN6_VERTSTRIDE_16 0x5 +#define GEN6_VERTSTRIDE_32 0x6 +#define GEN6_VERTSTRIDE_VXH 0xf +#define GEN6_WIDTH_1 0x0 +#define GEN6_WIDTH_2 0x1 +#define GEN6_WIDTH_4 0x2 +#define GEN6_WIDTH_8 0x3 +#define GEN6_WIDTH_16 0x4 +#define GEN6_HORZSTRIDE_0 0x0 +#define GEN6_HORZSTRIDE_1 0x1 +#define GEN6_HORZSTRIDE_2 0x2 +#define GEN6_HORZSTRIDE_4 0x3 +#define GEN6_ADDRMODE_DIRECT 0x0 +#define GEN6_ADDRMODE_INDIRECT 0x1 +#define GEN6_SWIZZLE_X 0x0 +#define GEN6_SWIZZLE_Y 0x1 +#define GEN6_SWIZZLE_Z 0x2 +#define GEN6_SWIZZLE_W 0x3 +#define GEN6_ARF_NULL 0x0 +#define GEN6_ARF_A0 0x10 +#define GEN6_ARF_ACC0 0x20 +#define GEN6_ARF_F0 0x30 +#define GEN6_ARF_SR0 0x70 +#define GEN6_ARF_CR0 0x80 +#define GEN6_ARF_N0 0x90 +#define GEN6_ARF_IP 0xa0 +#define GEN6_ARF_TDR 0xb0 +#define GEN7_ARF_TM0 0xc0 + +#define GEN6_INST_DW0_SATURATE (0x1 << 31) +#define GEN6_INST_DW0_ACCWRCTRL (0x1 << 28) +#define GEN6_INST_DW0_CONDMODIFIER__MASK 0x0f000000 +#define GEN6_INST_DW0_CONDMODIFIER__SHIFT 24 +#define GEN6_INST_DW0_SFID__MASK 0x0f000000 +#define GEN6_INST_DW0_SFID__SHIFT 24 +#define GEN6_INST_DW0_FC__MASK 0x0f000000 +#define GEN6_INST_DW0_FC__SHIFT 24 +#define GEN6_INST_DW0_EXECSIZE__MASK 0x00e00000 +#define GEN6_INST_DW0_EXECSIZE__SHIFT 21 +#define GEN6_INST_DW0_PREDINV (0x1 << 20) +#define GEN6_INST_DW0_PREDCTRL__MASK 0x000f0000 +#define GEN6_INST_DW0_PREDCTRL__SHIFT 16 +#define GEN6_INST_DW0_THREADCTRL__MASK 0x0000c000 +#define GEN6_INST_DW0_THREADCTRL__SHIFT 14 +#define GEN6_INST_DW0_QTRCTRL__MASK 0x00003000 +#define GEN6_INST_DW0_QTRCTRL__SHIFT 12 +#define GEN6_INST_DW0_DEPCTRL__MASK 0x00000c00 +#define GEN6_INST_DW0_DEPCTRL__SHIFT 10 +#define GEN6_INST_DW0_MASKCTRL__MASK 0x00000200 +#define GEN6_INST_DW0_MASKCTRL__SHIFT 9 +#define GEN6_INST_DW0_ACCESSMODE__MASK 0x00000100 +#define GEN6_INST_DW0_ACCESSMODE__SHIFT 8 +#define GEN6_INST_DW0_OPCODE__MASK 0x0000007f +#define GEN6_INST_DW0_OPCODE__SHIFT 0 + +#define GEN6_INST_DW1_ADDRMODE__MASK 0x80000000 +#define GEN6_INST_DW1_ADDRMODE__SHIFT 31 +#define GEN6_INST_DW1_HORZSTRIDE__MASK 0x60000000 +#define GEN6_INST_DW1_HORZSTRIDE__SHIFT 29 +#define GEN6_INST_DW1_REG__MASK 0x1fe00000 +#define GEN6_INST_DW1_REG__SHIFT 21 +#define GEN6_INST_DW1_SUBREG__MASK 0x001f0000 +#define GEN6_INST_DW1_SUBREG__SHIFT 16 +#define GEN6_INST_DW1_ADDR_SUBREG__MASK 0x1c000000 +#define GEN6_INST_DW1_ADDR_SUBREG__SHIFT 26 +#define GEN6_INST_DW1_ADDR_IMM__MASK 0x03ff0000 +#define GEN6_INST_DW1_ADDR_IMM__SHIFT 16 +#define GEN6_INST_DW1_SUBREG_ALIGN16__MASK 0x00100000 +#define GEN6_INST_DW1_SUBREG_ALIGN16__SHIFT 20 +#define GEN6_INST_DW1_SUBREG_ALIGN16__SHR 4 +#define GEN6_INST_DW1_ADDR_IMM_ALIGN16__MASK 0x03f00000 +#define GEN6_INST_DW1_ADDR_IMM_ALIGN16__SHIFT 20 +#define GEN6_INST_DW1_ADDR_IMM_ALIGN16__SHR 4 +#define GEN6_INST_DW1_WRITEMASK__MASK 0x000f0000 +#define GEN6_INST_DW1_WRITEMASK__SHIFT 16 +#define GEN7_INST_DW1_NIBCTRL (0x1 << 15) +#define GEN6_INST_DW1_SRC1_TYPE__MASK 0x00007000 +#define GEN6_INST_DW1_SRC1_TYPE__SHIFT 12 +#define GEN6_INST_DW1_SRC1_FILE__MASK 0x00000c00 +#define GEN6_INST_DW1_SRC1_FILE__SHIFT 10 +#define GEN6_INST_DW1_SRC0_TYPE__MASK 0x00000380 +#define GEN6_INST_DW1_SRC0_TYPE__SHIFT 7 +#define GEN6_INST_DW1_SRC0_FILE__MASK 0x00000060 +#define GEN6_INST_DW1_SRC0_FILE__SHIFT 5 +#define GEN6_INST_DW1_TYPE__MASK 0x0000001c +#define GEN6_INST_DW1_TYPE__SHIFT 2 +#define GEN6_INST_DW1_FILE__MASK 0x00000003 +#define GEN6_INST_DW1_FILE__SHIFT 0 + +#define GEN7_INST_DW2_FLAG_REG__MASK 0x04000000 +#define GEN7_INST_DW2_FLAG_REG__SHIFT 26 +#define GEN6_INST_DW2_FLAG_SUBREG__MASK 0x02000000 +#define GEN6_INST_DW2_FLAG_SUBREG__SHIFT 25 +#define GEN6_INST_DW2_VERTSTRIDE__MASK 0x01e00000 +#define GEN6_INST_DW2_VERTSTRIDE__SHIFT 21 +#define GEN6_INST_DW2_WIDTH__MASK 0x001c0000 +#define GEN6_INST_DW2_WIDTH__SHIFT 18 +#define GEN6_INST_DW2_HORZSTRIDE__MASK 0x00030000 +#define GEN6_INST_DW2_HORZSTRIDE__SHIFT 16 +#define GEN6_INST_DW2_SWIZZLE_W__MASK 0x000c0000 +#define GEN6_INST_DW2_SWIZZLE_W__SHIFT 18 +#define GEN6_INST_DW2_SWIZZLE_Z__MASK 0x00030000 +#define GEN6_INST_DW2_SWIZZLE_Z__SHIFT 16 +#define GEN6_INST_DW2_ADDRMODE__MASK 0x00008000 +#define GEN6_INST_DW2_ADDRMODE__SHIFT 15 +#define GEN6_INST_DW2_NEGATE (0x1 << 14) +#define GEN6_INST_DW2_ABSOLUTE (0x1 << 13) +#define GEN6_INST_DW2_REG__MASK 0x00001fe0 +#define GEN6_INST_DW2_REG__SHIFT 5 +#define GEN6_INST_DW2_SUBREG__MASK 0x0000001f +#define GEN6_INST_DW2_SUBREG__SHIFT 0 +#define GEN6_INST_DW2_ADDR_SUBREG__MASK 0x00001c00 +#define GEN6_INST_DW2_ADDR_SUBREG__SHIFT 10 +#define GEN6_INST_DW2_ADDR_IMM__MASK 0x000003ff +#define GEN6_INST_DW2_ADDR_IMM__SHIFT 0 +#define GEN6_INST_DW2_SUBREG_ALIGN16 (0x1 << 4) +#define GEN6_INST_DW2_SUBREG_ALIGN16__SHR 4 +#define GEN6_INST_DW2_ADDR_IMM_ALIGN16__MASK 0x000003f0 +#define GEN6_INST_DW2_ADDR_IMM_ALIGN16__SHIFT 4 +#define GEN6_INST_DW2_ADDR_IMM_ALIGN16__SHR 4 +#define GEN6_INST_DW2_SWIZZLE_Y__MASK 0x0000000c +#define GEN6_INST_DW2_SWIZZLE_Y__SHIFT 2 +#define GEN6_INST_DW2_SWIZZLE_X__MASK 0x00000003 +#define GEN6_INST_DW2_SWIZZLE_X__SHIFT 0 + +#define GEN7_INST_DW3_FLAG_REG__MASK 0x04000000 +#define GEN7_INST_DW3_FLAG_REG__SHIFT 26 +#define GEN6_INST_DW3_FLAG_SUBREG__MASK 0x02000000 +#define GEN6_INST_DW3_FLAG_SUBREG__SHIFT 25 +#define GEN6_INST_DW3_VERTSTRIDE__MASK 0x01e00000 +#define GEN6_INST_DW3_VERTSTRIDE__SHIFT 21 +#define GEN6_INST_DW3_WIDTH__MASK 0x001c0000 +#define GEN6_INST_DW3_WIDTH__SHIFT 18 +#define GEN6_INST_DW3_HORZSTRIDE__MASK 0x00030000 +#define GEN6_INST_DW3_HORZSTRIDE__SHIFT 16 +#define GEN6_INST_DW3_SWIZZLE_W__MASK 0x000c0000 +#define GEN6_INST_DW3_SWIZZLE_W__SHIFT 18 +#define GEN6_INST_DW3_SWIZZLE_Z__MASK 0x00030000 +#define GEN6_INST_DW3_SWIZZLE_Z__SHIFT 16 +#define GEN6_INST_DW3_ADDRMODE__MASK 0x00008000 +#define GEN6_INST_DW3_ADDRMODE__SHIFT 15 +#define GEN6_INST_DW3_NEGATE (0x1 << 14) +#define GEN6_INST_DW3_ABSOLUTE (0x1 << 13) +#define GEN6_INST_DW3_REG__MASK 0x00001fe0 +#define GEN6_INST_DW3_REG__SHIFT 5 +#define GEN6_INST_DW3_SUBREG__MASK 0x0000001f +#define GEN6_INST_DW3_SUBREG__SHIFT 0 +#define GEN6_INST_DW3_ADDR_SUBREG__MASK 0x00001c00 +#define GEN6_INST_DW3_ADDR_SUBREG__SHIFT 10 +#define GEN6_INST_DW3_ADDR_IMM__MASK 0x000003ff +#define GEN6_INST_DW3_ADDR_IMM__SHIFT 0 +#define GEN6_INST_DW3_SUBREG_ALIGN16 (0x1 << 4) +#define GEN6_INST_DW3_SUBREG_ALIGN16__SHR 4 +#define GEN6_INST_DW3_ADDR_IMM_ALIGN16__MASK 0x000003f0 +#define GEN6_INST_DW3_ADDR_IMM_ALIGN16__SHIFT 4 +#define GEN6_INST_DW3_ADDR_IMM_ALIGN16__SHR 4 +#define GEN6_INST_DW3_SWIZZLE_Y__MASK 0x0000000c +#define GEN6_INST_DW3_SWIZZLE_Y__SHIFT 2 +#define GEN6_INST_DW3_SWIZZLE_X__MASK 0x00000003 +#define GEN6_INST_DW3_SWIZZLE_X__SHIFT 0 + + +#define GEN6_3SRC_DW0_SATURATE (0x1 << 31) +#define GEN6_3SRC_DW0_ACCWRCTRL (0x1 << 28) +#define GEN6_3SRC_DW0_CONDMODIFIER__MASK 0x0f000000 +#define GEN6_3SRC_DW0_CONDMODIFIER__SHIFT 24 +#define GEN6_3SRC_DW0_SFID__MASK 0x0f000000 +#define GEN6_3SRC_DW0_SFID__SHIFT 24 +#define GEN6_3SRC_DW0_FC__MASK 0x0f000000 +#define GEN6_3SRC_DW0_FC__SHIFT 24 +#define GEN6_3SRC_DW0_EXECSIZE__MASK 0x00e00000 +#define GEN6_3SRC_DW0_EXECSIZE__SHIFT 21 +#define GEN6_3SRC_DW0_PREDINV (0x1 << 20) +#define GEN6_3SRC_DW0_PREDCTRL__MASK 0x000f0000 +#define GEN6_3SRC_DW0_PREDCTRL__SHIFT 16 +#define GEN6_3SRC_DW0_THREADCTRL__MASK 0x0000c000 +#define GEN6_3SRC_DW0_THREADCTRL__SHIFT 14 +#define GEN6_3SRC_DW0_QTRCTRL__MASK 0x00003000 +#define GEN6_3SRC_DW0_QTRCTRL__SHIFT 12 +#define GEN6_3SRC_DW0_DEPCTRL__MASK 0x00000c00 +#define GEN6_3SRC_DW0_DEPCTRL__SHIFT 10 +#define GEN6_3SRC_DW0_MASKCTRL__MASK 0x00000200 +#define GEN6_3SRC_DW0_MASKCTRL__SHIFT 9 +#define GEN6_3SRC_DW0_ACCESSMODE__MASK 0x00000100 +#define GEN6_3SRC_DW0_ACCESSMODE__SHIFT 8 +#define GEN6_3SRC_DW0_OPCODE__MASK 0x0000007f +#define GEN6_3SRC_DW0_OPCODE__SHIFT 0 + +#define GEN6_3SRC_DW1_REG__MASK 0xff000000 +#define GEN6_3SRC_DW1_REG__SHIFT 24 +#define GEN6_3SRC_DW1_SUBREG__MASK 0x00e00000 +#define GEN6_3SRC_DW1_SUBREG__SHIFT 21 +#define GEN6_3SRC_DW1_SUBREG__SHR 2 +#define GEN6_3SRC_DW1_WRITEMASK__MASK 0x001e0000 +#define GEN6_3SRC_DW1_WRITEMASK__SHIFT 17 +#define GEN7_3SRC_DW1_NIBCTRL (0x1 << 15) +#define GEN7_3SRC_DW1_TYPE__MASK 0x00003000 +#define GEN7_3SRC_DW1_TYPE__SHIFT 12 +#define GEN7_3SRC_DW1_SRC_TYPE__MASK 0x00000c00 +#define GEN7_3SRC_DW1_SRC_TYPE__SHIFT 10 +#define GEN6_3SRC_DW1_SRC2_NEGATE (0x1 << 9) +#define GEN6_3SRC_DW1_SRC2_ABSOLUTE (0x1 << 8) +#define GEN6_3SRC_DW1_SRC1_NEGATE (0x1 << 7) +#define GEN6_3SRC_DW1_SRC1_ABSOLUTE (0x1 << 6) +#define GEN6_3SRC_DW1_SRC0_NEGATE (0x1 << 5) +#define GEN6_3SRC_DW1_SRC0_ABSOLUTE (0x1 << 4) +#define GEN7_3SRC_DW1_FLAG_REG__MASK 0x00000004 +#define GEN7_3SRC_DW1_FLAG_REG__SHIFT 2 +#define GEN6_3SRC_DW1_FLAG_SUBREG__MASK 0x00000002 +#define GEN6_3SRC_DW1_FLAG_SUBREG__SHIFT 1 +#define GEN6_3SRC_DW1_FILE_MRF (0x1 << 0) + +#define GEN6_3SRC_SRC_2__MASK 0x7ffffc0000000000ULL +#define GEN6_3SRC_SRC_2__SHIFT 42 +#define GEN6_3SRC_SRC_2_REG__MASK 0x3fc0000000000000ULL +#define GEN6_3SRC_SRC_2_REG__SHIFT 54 +#define GEN6_3SRC_SRC_2_SUBREG__MASK 0x0038000000000000ULL +#define GEN6_3SRC_SRC_2_SUBREG__SHIFT 51 +#define GEN6_3SRC_SRC_2_SUBREG__SHR 2 +#define GEN6_3SRC_SRC_2_SWIZZLE_W__MASK 0x0006000000000000ULL +#define GEN6_3SRC_SRC_2_SWIZZLE_W__SHIFT 49 +#define GEN6_3SRC_SRC_2_SWIZZLE_Z__MASK 0x0001800000000000ULL +#define GEN6_3SRC_SRC_2_SWIZZLE_Z__SHIFT 47 +#define GEN6_3SRC_SRC_2_SWIZZLE_Y__MASK 0x0000600000000000ULL +#define GEN6_3SRC_SRC_2_SWIZZLE_Y__SHIFT 45 +#define GEN6_3SRC_SRC_2_SWIZZLE_X__MASK 0x0000180000000000ULL +#define GEN6_3SRC_SRC_2_SWIZZLE_X__SHIFT 43 +#define GEN6_3SRC_SRC_2_REPCTRL (0x1 << 42) +#define GEN6_3SRC_SRC_1__MASK 0x000003ffffe00000ULL +#define GEN6_3SRC_SRC_1__SHIFT 21 +#define GEN6_3SRC_SRC_1_REG__MASK 0x000001fe00000000ULL +#define GEN6_3SRC_SRC_1_REG__SHIFT 33 +#define GEN6_3SRC_SRC_1_SUBREG__MASK 0x00000001c0000000ULL +#define GEN6_3SRC_SRC_1_SUBREG__SHIFT 30 +#define GEN6_3SRC_SRC_1_SUBREG__SHR 2 +#define GEN6_3SRC_SRC_1_SWIZZLE_W__MASK 0x30000000 +#define GEN6_3SRC_SRC_1_SWIZZLE_W__SHIFT 28 +#define GEN6_3SRC_SRC_1_SWIZZLE_Z__MASK 0x0c000000 +#define GEN6_3SRC_SRC_1_SWIZZLE_Z__SHIFT 26 +#define GEN6_3SRC_SRC_1_SWIZZLE_Y__MASK 0x03000000 +#define GEN6_3SRC_SRC_1_SWIZZLE_Y__SHIFT 24 +#define GEN6_3SRC_SRC_1_SWIZZLE_X__MASK 0x00c00000 +#define GEN6_3SRC_SRC_1_SWIZZLE_X__SHIFT 22 +#define GEN6_3SRC_SRC_1_REPCTRL (0x1 << 21) +#define GEN6_3SRC_SRC_0__MASK 0x001fffff +#define GEN6_3SRC_SRC_0__SHIFT 0 +#define GEN6_3SRC_SRC_0_REG__MASK 0x000ff000 +#define GEN6_3SRC_SRC_0_REG__SHIFT 12 +#define GEN6_3SRC_SRC_0_SUBREG__MASK 0x00000e00 +#define GEN6_3SRC_SRC_0_SUBREG__SHIFT 9 +#define GEN6_3SRC_SRC_0_SUBREG__SHR 2 +#define GEN6_3SRC_SRC_0_SWIZZLE_W__MASK 0x00000180 +#define GEN6_3SRC_SRC_0_SWIZZLE_W__SHIFT 7 +#define GEN6_3SRC_SRC_0_SWIZZLE_Z__MASK 0x00000060 +#define GEN6_3SRC_SRC_0_SWIZZLE_Z__SHIFT 5 +#define GEN6_3SRC_SRC_0_SWIZZLE_Y__MASK 0x00000018 +#define GEN6_3SRC_SRC_0_SWIZZLE_Y__SHIFT 3 +#define GEN6_3SRC_SRC_0_SWIZZLE_X__MASK 0x00000006 +#define GEN6_3SRC_SRC_0_SWIZZLE_X__SHIFT 1 +#define GEN6_3SRC_SRC_0_REPCTRL (0x1 << 0) + + +#endif /* GEN_EU_ISA_XML */ diff --git a/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h b/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h new file mode 100644 index 00000000000..36f2097e12b --- /dev/null +++ b/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h @@ -0,0 +1,219 @@ +#ifndef GEN_EU_MESSAGE_XML +#define GEN_EU_MESSAGE_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +https://github.com/olvaffe/envytools/ +git clone https://github.com/olvaffe/envytools.git + +Copyright (C) 2014 by the following authors: +- Chia-I Wu <[email protected]> (olv) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define GEN6_MSG_URB_WRITE 0x0 +#define GEN6_MSG_URB_FF_SYNC 0x1 +#define GEN7_MSG_URB_WRITE_HWORD 0x0 +#define GEN7_MSG_URB_WRITE_OWORD 0x1 +#define GEN7_MSG_URB_READ_HWORD 0x2 +#define GEN7_MSG_URB_READ_OWORD 0x3 +#define GEN7_MSG_URB_ATOMIC_MOV 0x4 +#define GEN7_MSG_URB_ATOMIC_INC 0x5 +#define GEN6_MSG_SAMPLER_SIMD4X2 0x0 +#define GEN6_MSG_SAMPLER_SIMD8 0x1 +#define GEN6_MSG_SAMPLER_SIMD16 0x2 +#define GEN6_MSG_SAMPLER_SIMD32_64 0x3 +#define GEN6_MSG_SAMPLER_SAMPLE 0x0 +#define GEN6_MSG_SAMPLER_SAMPLE_B 0x1 +#define GEN6_MSG_SAMPLER_SAMPLE_L 0x2 +#define GEN6_MSG_SAMPLER_SAMPLE_C 0x3 +#define GEN6_MSG_SAMPLER_SAMPLE_D 0x4 +#define GEN6_MSG_SAMPLER_SAMPLE_B_C 0x5 +#define GEN6_MSG_SAMPLER_SAMPLE_L_C 0x6 +#define GEN6_MSG_SAMPLER_LD 0x7 +#define GEN6_MSG_SAMPLER_GATHER4 0x8 +#define GEN6_MSG_SAMPLER_LOD 0x9 +#define GEN6_MSG_SAMPLER_RESINFO 0xa +#define GEN6_MSG_SAMPLER_SAMPLEINFO 0xb +#define GEN7_MSG_SAMPLER_GATHER4_C 0x10 +#define GEN7_MSG_SAMPLER_GATHER4_PO 0x11 +#define GEN7_MSG_SAMPLER_GATHER4_PO_C 0x12 +#define GEN7_MSG_SAMPLER_SAMPLE_D_C 0x14 +#define GEN7_MSG_SAMPLER_SAMPLE_LZ 0x18 +#define GEN7_MSG_SAMPLER_SAMPLE_C_LC 0x19 +#define GEN7_MSG_SAMPLER_SAMPLE_LD_LZ 0x1a +#define GEN7_MSG_SAMPLER_LD_MCS 0x1d +#define GEN7_MSG_SAMPLER_LD2DMS 0x1e +#define GEN7_MSG_SAMPLER_LD2DSS 0x1f +#define GEN6_MSG_DP_OWORD_BLOCK_READ 0x0 +#define GEN6_MSG_DP_RT_UNORM_READ 0x1 +#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_READ 0x2 +#define GEN6_MSG_DP_MEDIA_BLOCK_READ 0x4 +#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_READ 0x5 +#define GEN6_MSG_DP_DWORD_SCATTERED_READ 0x6 +#define GEN6_MSG_DP_DWORD_ATOMIC_WRITE 0x7 +#define GEN6_MSG_DP_OWORD_BLOCK_WRITE 0x8 +#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_WRITE 0x9 +#define GEN6_MSG_DP_MEDIA_BLOCK_WRITE 0xa +#define GEN6_MSG_DP_DWORD_SCATTERED_WRITE 0xb +#define GEN6_MSG_DP_RT_WRITE 0xc +#define GEN6_MSG_DP_SVB_WRITE 0xd +#define GEN6_MSG_DP_RT_UNORM_WRITE 0xe +#define GEN7_MSG_DP_SAMPLER_OWORD_BLOCK_READ 0x1 +#define GEN7_MSG_DP_SAMPLER_MEDIA_BLOCK_READ 0x4 +#define GEN7_MSG_DP_RC_MEDIA_BLOCK_READ 0x4 +#define GEN7_MSG_DP_RC_TYPED_SURFACE_READ 0x5 +#define GEN7_MSG_DP_RC_TYPED_ATOMIC_OP 0x6 +#define GEN7_MSG_DP_RC_MEMORY_FENCE 0x7 +#define GEN7_MSG_DP_RC_MEDIA_BLOCK_WRITE 0xa +#define GEN7_MSG_DP_RC_RT_WRITE 0xc +#define GEN7_MSG_DP_RC_TYPED_SURFACE_WRITE 0xd +#define GEN7_MSG_DP_CC_OWORD_BLOCK_READ 0x0 +#define GEN7_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ 0x1 +#define GEN7_MSG_DP_CC_OWORD_DUAL_BLOCK_READ 0x2 +#define GEN7_MSG_DP_CC_DWORD_SCATTERED_READ 0x3 +#define GEN7_MSG_DP_DC0_OWORD_BLOCK_READ 0x0 +#define GEN7_MSG_DP_DC0_UNALIGNED_OWORD_BLOCK_READ 0x1 +#define GEN7_MSG_DP_DC0_OWORD_DUAL_BLOCK_READ 0x2 +#define GEN7_MSG_DP_DC0_DWORD_SCATTERED_READ 0x3 +#define GEN7_MSG_DP_DC0_BYTE_SCATTERED_READ 0x4 +#define GEN7_MSG_DP_DC0_UNTYPED_SURFACE_READ 0x5 +#define GEN7_MSG_DP_DC0_UNTYPED_ATOMIC_OP 0x6 +#define GEN7_MSG_DP_DC0_MEMORY_FENCE 0x7 +#define GEN7_MSG_DP_DC0_OWORD_BLOCK_WRITE 0x8 +#define GEN7_MSG_DP_DC0_OWORD_DUAL_BLOCK_WRITE 0xa +#define GEN7_MSG_DP_DC0_DWORD_SCATTERED_WRITE 0xb +#define GEN7_MSG_DP_DC0_BYTE_SCATTERED_WRITE 0xc +#define GEN7_MSG_DP_DC0_UNTYPED_SURFACE_WRITE 0xd +#define GEN75_MSG_DP_SAMPLER_READ_SURFACE_INFO 0x0 +#define GEN75_MSG_DP_SAMPLER_UNALIGNED_OWORD_BLOCK_READ 0x1 +#define GEN75_MSG_DP_SAMPLER_MEDIA_BLOCK_READ 0x4 +#define GEN75_MSG_DP_RC_MEDIA_BLOCK_READ 0x4 +#define GEN75_MSG_DP_RC_MEMORY_FENCE 0x7 +#define GEN75_MSG_DP_RC_MEDIA_BLOCK_WRITE 0xa +#define GEN75_MSG_DP_RC_RT_WRITE 0xc +#define GEN75_MSG_DP_CC_OWORD_BLOCK_READ 0x0 +#define GEN75_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ 0x1 +#define GEN75_MSG_DP_CC_OWORD_DUAL_BLOCK_READ 0x2 +#define GEN75_MSG_DP_CC_DWORD_SCATTERED_READ 0x3 +#define GEN75_MSG_DP_DC0_OWORD_BLOCK_READ 0x0 +#define GEN75_MSG_DP_DC0_UNALIGNED_OWORD_BLOCK_READ 0x1 +#define GEN75_MSG_DP_DC0_OWORD_DUAL_BLOCK_READ 0x2 +#define GEN75_MSG_DP_DC0_DWORD_SCATTERED_READ 0x3 +#define GEN75_MSG_DP_DC0_BYTE_SCATTERED_READ 0x4 +#define GEN75_MSG_DP_DC0_MEMORY_FENCE 0x7 +#define GEN75_MSG_DP_DC0_OWORD_BLOCK_WRITE 0x8 +#define GEN75_MSG_DP_DC0_OWORD_DUAL_BLOCK_WRITE 0xa +#define GEN75_MSG_DP_DC0_DWORD_SCATTERED_WRITE 0xb +#define GEN75_MSG_DP_DC0_BYTE_SCATTERED_WRITE 0xc +#define GEN75_MSG_DP_DC1_UNTYPED_SURFACE_READ 0x1 +#define GEN75_MSG_DP_DC1_UNTYPED_ATOMIC_OP 0x2 +#define GEN75_MSG_DP_DC1_UNTYPED_ATOMIC_OP_SIMD4X2 0x3 +#define GEN75_MSG_DP_DC1_MEDIA_BLOCK_READ 0x4 +#define GEN75_MSG_DP_DC1_TYPED_SURFACE_READ 0x5 +#define GEN75_MSG_DP_DC1_TYPED_ATOMIC_OP 0x6 +#define GEN75_MSG_DP_DC1_TYPED_ATOMIC_OP_SIMD4X2 0x7 +#define GEN75_MSG_DP_DC1_UNTYPED_SURFACE_WRITE 0x9 +#define GEN75_MSG_DP_DC1_MEDIA_BLOCK_WRITE 0xa +#define GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP 0xb +#define GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP_SIMD4X2 0xc +#define GEN75_MSG_DP_DC1_TYPED_SURFACE_WRITE 0xd +#define GEN6_MSG_EOT (0x1 << 31) +#define GEN6_MSG_MLEN__MASK 0x1e000000 +#define GEN6_MSG_MLEN__SHIFT 25 +#define GEN6_MSG_RLEN__MASK 0x01f00000 +#define GEN6_MSG_RLEN__SHIFT 20 +#define GEN6_MSG_HEADER_PRESENT (0x1 << 19) +#define GEN6_MSG_FUNCTION_CONTROL__MASK 0x0007ffff +#define GEN6_MSG_FUNCTION_CONTROL__SHIFT 0 +#define GEN6_MSG_URB_COMPLETE (0x1 << 15) +#define GEN6_MSG_URB_USED (0x1 << 14) +#define GEN6_MSG_URB_ALLOCATE (0x1 << 13) +#define GEN6_MSG_URB_INTERLEAVED (0x1 << 10) +#define GEN6_MSG_URB_OFFSET__MASK 0x000003f0 +#define GEN6_MSG_URB_OFFSET__SHIFT 4 +#define GEN6_MSG_URB_OP__MASK 0x0000000f +#define GEN6_MSG_URB_OP__SHIFT 0 +#define GEN7_MSG_URB_PER_SLOT_OFFSET (0x1 << 16) +#define GEN7_MSG_URB_COMPLETE (0x1 << 15) +#define GEN7_MSG_URB_INTERLEAVED (0x1 << 14) +#define GEN7_MSG_URB_GLOBAL_OFFSET__MASK 0x00003ff8 +#define GEN7_MSG_URB_GLOBAL_OFFSET__SHIFT 3 +#define GEN7_MSG_URB_OP__MASK 0x00000007 +#define GEN7_MSG_URB_OP__SHIFT 0 +#define GEN6_MSG_SAMPLER_SIMD__MASK 0x00030000 +#define GEN6_MSG_SAMPLER_SIMD__SHIFT 16 +#define GEN6_MSG_SAMPLER_OP__MASK 0x0000f000 +#define GEN6_MSG_SAMPLER_OP__SHIFT 12 +#define GEN7_MSG_SAMPLER_SIMD__MASK 0x00060000 +#define GEN7_MSG_SAMPLER_SIMD__SHIFT 17 +#define GEN7_MSG_SAMPLER_OP__MASK 0x0001f000 +#define GEN7_MSG_SAMPLER_OP__SHIFT 12 +#define GEN6_MSG_SAMPLER_INDEX__MASK 0x00000f00 +#define GEN6_MSG_SAMPLER_INDEX__SHIFT 8 +#define GEN6_MSG_SAMPLER_SURFACE__MASK 0x000000ff +#define GEN6_MSG_SAMPLER_SURFACE__SHIFT 0 +#define GEN6_MSG_DP_SEND_WRITE_COMMIT (0x1 << 17) +#define GEN6_MSG_DP_OP__MASK 0x0001e000 +#define GEN6_MSG_DP_OP__SHIFT 13 +#define GEN7_MSG_DP_CATEGORY (0x1 << 18) +#define GEN7_MSG_DP_OP__MASK 0x0003c000 +#define GEN7_MSG_DP_OP__SHIFT 14 +#define GEN7_MSG_DP_OWORD_BLOCK_READ_INVALIDATE (0x1 << 13) +#define GEN6_MSG_DP_OWORD_BLOCK_SIZE__MASK 0x00000700 +#define GEN6_MSG_DP_OWORD_BLOCK_SIZE__SHIFT 8 +#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_LO (0x0 << 8) +#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_HI (0x1 << 8) +#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_2 (0x2 << 8) +#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_4 (0x3 << 8) +#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_8 (0x4 << 8) +#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE__MASK 0x00000700 +#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE__SHIFT 8 +#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_1_LO (0x0 << 8) +#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_1_HI (0x1 << 8) +#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_2 (0x2 << 8) +#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_4 (0x3 << 8) +#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_8 (0x4 << 8) +#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE__MASK 0x00000300 +#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE__SHIFT 8 +#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_1 (0x0 << 8) +#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_4 (0x2 << 8) +#define GEN7_MSG_DP_DWORD_SCATTERED_READ_INVALIDATE (0x1 << 13) +#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE__MASK 0x00000300 +#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE__SHIFT 8 +#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE_8 (0x2 << 8) +#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE_16 (0x3 << 8) +#define GEN6_MSG_DP_RT_LAST (0x1 << 12) +#define GEN6_MSG_DP_RT_MODE__MASK 0x00000700 +#define GEN6_MSG_DP_RT_MODE__SHIFT 8 +#define GEN6_MSG_DP_RT_MODE_SIMD16 (0x0 << 8) +#define GEN6_MSG_DP_RT_MODE_SIMD16_REPDATA (0x1 << 8) +#define GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_LO (0x2 << 8) +#define GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_HI (0x3 << 8) +#define GEN6_MSG_DP_RT_MODE_SIMD8_LO (0x4 << 8) +#define GEN6_MSG_DP_RT_MODE_SIMD8_IMAGE_WR (0x5 << 8) +#define GEN6_MSG_DP_SURFACE__MASK 0x000000ff +#define GEN6_MSG_DP_SURFACE__SHIFT 0 + +#endif /* GEN_EU_MESSAGE_XML */ diff --git a/src/gallium/drivers/ilo/genhw/gen_mi.xml.h b/src/gallium/drivers/ilo/genhw/gen_mi.xml.h new file mode 100644 index 00000000000..219ddab2653 --- /dev/null +++ b/src/gallium/drivers/ilo/genhw/gen_mi.xml.h @@ -0,0 +1,120 @@ +#ifndef GEN_MI_XML +#define GEN_MI_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +https://github.com/olvaffe/envytools/ +git clone https://github.com/olvaffe/envytools.git + +Copyright (C) 2014 by the following authors: +- Chia-I Wu <[email protected]> (olv) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define GEN6_MI_TYPE__MASK 0xe0000000 +#define GEN6_MI_TYPE__SHIFT 29 +#define GEN6_MI_TYPE_MI (0x0 << 29) +#define GEN6_MI_OPCODE__MASK 0x1f800000 +#define GEN6_MI_OPCODE__SHIFT 23 +#define GEN6_MI_OPCODE_MI_NOOP (0x0 << 23) +#define GEN6_MI_OPCODE_MI_BATCH_BUFFER_END (0xa << 23) +#define GEN6_MI_OPCODE_MI_STORE_DATA_IMM (0x20 << 23) +#define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM (0x22 << 23) +#define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM (0x24 << 23) +#define GEN6_MI_OPCODE_MI_FLUSH_DW (0x26 << 23) +#define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT (0x28 << 23) +#define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM (0x29 << 23) +#define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START (0x31 << 23) +#define GEN6_MI_LENGTH__MASK 0x0000003f +#define GEN6_MI_LENGTH__SHIFT 0 +#define GEN6_MI_NOOP__SIZE 1 + +#define GEN6_MI_BATCH_BUFFER_END__SIZE 1 + +#define GEN6_MI_STORE_DATA_IMM__SIZE 5 +#define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22) + +#define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc +#define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHIFT 2 +#define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHR 2 + + +#define GEN6_MI_LOAD_REGISTER_IMM__SIZE 3 +#define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__MASK 0x00000f00 +#define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__SHIFT 8 + +#define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__MASK 0x007ffffc +#define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHIFT 2 +#define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHR 2 + + +#define GEN6_MI_STORE_REGISTER_MEM__SIZE 3 +#define GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22) +#define GEN75_MI_STORE_REGISTER_MEM_DW0_PREDICATE_ENABLE (0x1 << 21) + +#define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__MASK 0x007ffffc +#define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHIFT 2 +#define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHR 2 + +#define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__MASK 0xfffffffc +#define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHIFT 2 +#define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR 2 + +#define GEN6_MI_FLUSH_DW__SIZE 4 + +#define GEN6_MI_REPORT_PERF_COUNT__SIZE 3 + +#define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__MASK 0xffffffc0 +#define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHIFT 6 +#define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHR 6 +#define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE (0x1 << 4) +#define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT (0x1 << 0) + + +#define GEN7_MI_LOAD_REGISTER_MEM__SIZE 3 +#define GEN7_MI_LOAD_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22) +#define GEN7_MI_LOAD_REGISTER_MEM_DW0_ASYNC_MODE_ENABLE (0x1 << 21) + +#define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__MASK 0x007ffffc +#define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHIFT 2 +#define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHR 2 + +#define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__MASK 0xfffffffc +#define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHIFT 2 +#define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHR 2 + +#define GEN6_MI_BATCH_BUFFER_START__SIZE 2 +#define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL (0x1 << 22) +#define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE (0x1 << 16) +#define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE (0x1 << 15) +#define GEN75_MI_BATCH_BUFFER_START_DW0_NON_PRIVILEGED (0x1 << 13) +#define GEN6_MI_BATCH_BUFFER_START_DW0_CLEAR_COMMAND_BUFFER (0x1 << 11) +#define GEN6_MI_BATCH_BUFFER_START_DW0_USE_PPGTT (0x1 << 8) + +#define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__MASK 0xfffffffc +#define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHIFT 2 +#define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHR 2 + + +#endif /* GEN_MI_XML */ diff --git a/src/gallium/drivers/ilo/genhw/gen_regs.xml.h b/src/gallium/drivers/ilo/genhw/gen_regs.xml.h new file mode 100644 index 00000000000..4c59b219765 --- /dev/null +++ b/src/gallium/drivers/ilo/genhw/gen_regs.xml.h @@ -0,0 +1,65 @@ +#ifndef GEN_REGS_XML +#define GEN_REGS_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +https://github.com/olvaffe/envytools/ +git clone https://github.com/olvaffe/envytools.git + +Copyright (C) 2014 by the following authors: +- Chia-I Wu <[email protected]> (olv) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define GEN6_REG_MASK__MASK 0xffff0000 +#define GEN6_REG_MASK__SHIFT 16 +#define GEN6_REG__SIZE 0x400000 +#define GEN6_REG_HS_INVOCATION_COUNT 0x2300 + +#define GEN6_REG_DS_INVOCATION_COUNT 0x2308 + +#define GEN6_REG_IA_VERTICES_COUNT 0x2310 + +#define GEN6_REG_IA_PRIMITIVES_COUNT 0x2318 + +#define GEN6_REG_VS_INVOCATION_COUNT 0x2320 + +#define GEN6_REG_GS_INVOCATION_COUNT 0x2328 + +#define GEN6_REG_GS_PRIMITIVES_COUNT 0x2330 + +#define GEN6_REG_CL_INVOCATION_COUNT 0x2338 + +#define GEN6_REG_CL_PRIMITIVES_COUNT 0x2340 + +#define GEN6_REG_PS_INVOCATION_COUNT 0x2348 + +#define GEN6_REG_TIMESTAMP 0x2358 + +#define GEN6_REG_BCS_SWCTRL 0x22200 +#define GEN6_REG_BCS_SWCTRL_DST_TILING_Y (0x1 << 1) +#define GEN6_REG_BCS_SWCTRL_SRC_TILING_Y (0x1 << 0) + + +#endif /* GEN_REGS_XML */ diff --git a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h new file mode 100644 index 00000000000..efbede7f1fd --- /dev/null +++ b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h @@ -0,0 +1,1430 @@ +#ifndef GEN_RENDER_3D_XML +#define GEN_RENDER_3D_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +https://github.com/olvaffe/envytools/ +git clone https://github.com/olvaffe/envytools.git + +Copyright (C) 2014 by the following authors: +- Chia-I Wu <[email protected]> (olv) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define GEN6_3DPRIM_POINTLIST 0x1 +#define GEN6_3DPRIM_LINELIST 0x2 +#define GEN6_3DPRIM_LINESTRIP 0x3 +#define GEN6_3DPRIM_TRILIST 0x4 +#define GEN6_3DPRIM_TRISTRIP 0x5 +#define GEN6_3DPRIM_TRIFAN 0x6 +#define GEN6_3DPRIM_QUADLIST 0x7 +#define GEN6_3DPRIM_QUADSTRIP 0x8 +#define GEN6_3DPRIM_LINELIST_ADJ 0x9 +#define GEN6_3DPRIM_LINESTRIP_ADJ 0xa +#define GEN6_3DPRIM_TRILIST_ADJ 0xb +#define GEN6_3DPRIM_TRISTRIP_ADJ 0xc +#define GEN6_3DPRIM_TRISTRIP_REVERSE 0xd +#define GEN6_3DPRIM_POLYGON 0xe +#define GEN6_3DPRIM_RECTLIST 0xf +#define GEN6_3DPRIM_LINELOOP 0x10 +#define GEN6_3DPRIM_POINTLIST_BF 0x11 +#define GEN6_3DPRIM_LINESTRIP_CONT 0x12 +#define GEN6_3DPRIM_LINESTRIP_BF 0x13 +#define GEN6_3DPRIM_LINESTRIP_CONT_BF 0x14 +#define GEN6_3DPRIM_TRIFAN_NOSTIPPLE 0x16 +#define GEN7_3DPRIM_PATCHLIST_1 0x20 +#define GEN7_3DPRIM_PATCHLIST_2 0x21 +#define GEN7_3DPRIM_PATCHLIST_3 0x22 +#define GEN7_3DPRIM_PATCHLIST_4 0x23 +#define GEN7_3DPRIM_PATCHLIST_5 0x24 +#define GEN7_3DPRIM_PATCHLIST_6 0x25 +#define GEN7_3DPRIM_PATCHLIST_7 0x26 +#define GEN7_3DPRIM_PATCHLIST_8 0x27 +#define GEN7_3DPRIM_PATCHLIST_9 0x28 +#define GEN7_3DPRIM_PATCHLIST_10 0x29 +#define GEN7_3DPRIM_PATCHLIST_11 0x2a +#define GEN7_3DPRIM_PATCHLIST_12 0x2b +#define GEN7_3DPRIM_PATCHLIST_13 0x2c +#define GEN7_3DPRIM_PATCHLIST_14 0x2d +#define GEN7_3DPRIM_PATCHLIST_15 0x2e +#define GEN7_3DPRIM_PATCHLIST_16 0x2f +#define GEN7_3DPRIM_PATCHLIST_17 0x30 +#define GEN7_3DPRIM_PATCHLIST_18 0x31 +#define GEN7_3DPRIM_PATCHLIST_19 0x32 +#define GEN7_3DPRIM_PATCHLIST_20 0x33 +#define GEN7_3DPRIM_PATCHLIST_21 0x34 +#define GEN7_3DPRIM_PATCHLIST_22 0x35 +#define GEN7_3DPRIM_PATCHLIST_23 0x36 +#define GEN7_3DPRIM_PATCHLIST_24 0x37 +#define GEN7_3DPRIM_PATCHLIST_25 0x38 +#define GEN7_3DPRIM_PATCHLIST_26 0x39 +#define GEN7_3DPRIM_PATCHLIST_27 0x3a +#define GEN7_3DPRIM_PATCHLIST_28 0x3b +#define GEN7_3DPRIM_PATCHLIST_29 0x3c +#define GEN7_3DPRIM_PATCHLIST_30 0x3d +#define GEN7_3DPRIM_PATCHLIST_31 0x3e +#define GEN7_3DPRIM_PATCHLIST_32 0x3f +#define GEN6_ALIGNMENT_COLOR_CALC_STATE 0x10 +#define GEN6_ALIGNMENT_DEPTH_STENCIL_STATE 0x10 +#define GEN6_ALIGNMENT_BLEND_STATE 0x10 +#define GEN6_ALIGNMENT_CLIP_VIEWPORT 0x8 +#define GEN6_ALIGNMENT_SF_VIEWPORT 0x8 +#define GEN7_ALIGNMENT_SF_CLIP_VIEWPORT 0x10 +#define GEN6_ALIGNMENT_CC_VIEWPORT 0x8 +#define GEN6_ALIGNMENT_SCISSOR_RECT 0x8 +#define GEN6_ALIGNMENT_BINDING_TABLE_STATE 0x8 +#define GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR 0x8 +#define GEN6_ALIGNMENT_SAMPLER_STATE 0x8 +#define GEN6_ALIGNMENT_SURFACE_STATE 0x8 +#define GEN6_VFCOMP_NOSTORE 0x0 +#define GEN6_VFCOMP_STORE_SRC 0x1 +#define GEN6_VFCOMP_STORE_0 0x2 +#define GEN6_VFCOMP_STORE_1_FP 0x3 +#define GEN6_VFCOMP_STORE_1_INT 0x4 +#define GEN6_VFCOMP_STORE_VID 0x5 +#define GEN6_VFCOMP_STORE_IID 0x6 +#define GEN6_ZFORMAT_D32_FLOAT_S8X24_UINT 0x0 +#define GEN6_ZFORMAT_D32_FLOAT 0x1 +#define GEN6_ZFORMAT_D24_UNORM_S8_UINT 0x2 +#define GEN6_ZFORMAT_D24_UNORM_X8_UINT 0x3 +#define GEN6_ZFORMAT_D16_UNORM 0x5 +#define GEN6_RENDER_TYPE__MASK 0xe0000000 +#define GEN6_RENDER_TYPE__SHIFT 29 +#define GEN6_RENDER_TYPE_RENDER (0x3 << 29) +#define GEN6_RENDER_SUBTYPE__MASK 0x18000000 +#define GEN6_RENDER_SUBTYPE__SHIFT 27 +#define GEN6_RENDER_SUBTYPE_COMMON (0x0 << 27) +#define GEN6_RENDER_SUBTYPE_SINGLE_DW (0x1 << 27) +#define GEN6_RENDER_SUBTYPE_MEDIA (0x2 << 27) +#define GEN6_RENDER_SUBTYPE_3D (0x3 << 27) +#define GEN6_RENDER_OPCODE__MASK 0x07ff0000 +#define GEN6_RENDER_OPCODE__SHIFT 16 +#define GEN6_RENDER_OPCODE_STATE_BASE_ADDRESS (0x101 << 16) +#define GEN6_RENDER_OPCODE_STATE_SIP (0x102 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_VF_STATISTICS (0xb << 16) +#define GEN6_RENDER_OPCODE_PIPELINE_SELECT (0x104 << 16) +#define GEN6_RENDER_OPCODE_MEDIA_VFE_STATE (0x0 << 16) +#define GEN6_RENDER_OPCODE_MEDIA_CURBE_LOAD (0x1 << 16) +#define GEN6_RENDER_OPCODE_MEDIA_INTERFACE_DESCRIPTOR_LOAD (0x2 << 16) +#define GEN6_RENDER_OPCODE_MEDIA_GATEWAY_STATE (0x3 << 16) +#define GEN6_RENDER_OPCODE_MEDIA_STATE_FLUSH (0x4 << 16) +#define GEN6_RENDER_OPCODE_MEDIA_OBJECT_WALKER (0x103 << 16) +#define GEN7_RENDER_OPCODE_GPGPU_WALKER (0x105 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS (0x1 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS (0x2 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_CLEAR_PARAMS (0x4 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_URB (0x5 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x5 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_STENCIL_BUFFER (0x6 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_HIER_DEPTH_BUFFER (0x7 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_VERTEX_BUFFERS (0x8 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_VERTEX_ELEMENTS (0x9 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_INDEX_BUFFER (0xa << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_VF (0xc << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS (0xd << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS (0xe << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS (0xf << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_VS (0x10 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_GS (0x11 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_CLIP (0x12 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_SF (0x13 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_WM (0x14 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS (0x15 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS (0x16 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS (0x17 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_SAMPLE_MASK (0x18 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_HS (0x19 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS (0x1a << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_HS (0x1b << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_TE (0x1c << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_DS (0x1d << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_STREAMOUT (0x1e << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_SBE (0x1f << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_PS (0x20 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP (0x21 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC (0x23 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS (0x24 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS (0x25 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS (0x26 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_HS (0x27 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_DS (0x28 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_GS (0x29 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS (0x2a << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_VS (0x2b << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_HS (0x2c << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_DS (0x2d << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_GS (0x2e << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS (0x2f << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_URB_VS (0x30 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_URB_HS (0x31 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_URB_DS (0x32 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_URB_GS (0x33 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_DRAWING_RECTANGLE (0x100 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x105 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_OFFSET (0x106 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_PATTERN (0x107 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_LINE_STIPPLE (0x108 << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_AA_LINE_PARAMETERS (0x10a << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_GS_SVB_INDEX (0x10b << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_MULTISAMPLE (0x10d << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_STENCIL_BUFFER (0x10e << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_HIER_DEPTH_BUFFER (0x10f << 16) +#define GEN6_RENDER_OPCODE_3DSTATE_CLEAR_PARAMS (0x110 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_VS (0x112 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_HS (0x113 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_DS (0x114 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_GS (0x115 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS (0x116 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_SO_DECL_LIST (0x117 << 16) +#define GEN7_RENDER_OPCODE_3DSTATE_SO_BUFFER (0x118 << 16) +#define GEN6_RENDER_OPCODE_PIPE_CONTROL (0x200 << 16) +#define GEN6_RENDER_OPCODE_3DPRIMITIVE (0x300 << 16) +#define GEN6_RENDER_LENGTH__MASK 0x000000ff +#define GEN6_RENDER_LENGTH__SHIFT 0 +#define GEN6_INTERP_NONPERSPECTIVE_SAMPLE (0x1 << 5) +#define GEN6_INTERP_NONPERSPECTIVE_CENTROID (0x1 << 4) +#define GEN6_INTERP_NONPERSPECTIVE_PIXEL (0x1 << 3) +#define GEN6_INTERP_PERSPECTIVE_SAMPLE (0x1 << 2) +#define GEN6_INTERP_PERSPECTIVE_CENTROID (0x1 << 1) +#define GEN6_INTERP_PERSPECTIVE_PIXEL (0x1 << 0) +#define GEN6_THREADDISP_SPF (0x1 << 31) +#define GEN6_THREADDISP_VME (0x1 << 30) +#define GEN6_THREADDISP_SAMPLER_COUNT__MASK 0x38000000 +#define GEN6_THREADDISP_SAMPLER_COUNT__SHIFT 27 +#define GEN7_THREADDISP_DENORMAL__MASK 0x04000000 +#define GEN7_THREADDISP_DENORMAL__SHIFT 26 +#define GEN7_THREADDISP_DENORMAL_FTZ (0x0 << 26) +#define GEN7_THREADDISP_DENORMAL_RET (0x1 << 26) +#define GEN6_THREADDISP_BINDING_TABLE_SIZE__MASK 0x03fc0000 +#define GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT 18 +#define GEN6_THREADDISP_PRIORITY_HIGH (0x1 << 17) +#define GEN6_THREADDISP_FP_MODE_ALT (0x1 << 16) +#define GEN7_ROUNDING_MODE__MASK 0x0000c000 +#define GEN7_ROUNDING_MODE__SHIFT 14 +#define GEN7_ROUNDING_MODE_RTNE (0x0 << 14) +#define GEN7_ROUNDING_MODE_RU (0x1 << 14) +#define GEN7_ROUNDING_MODE_RD (0x2 << 14) +#define GEN7_ROUNDING_MODE_RTZ (0x3 << 14) +#define GEN6_THREADDISP_ILLEGAL_CODE_EXCEPTION (0x1 << 13) +#define GEN75_THREADDISP_ACCESS_UAV (0x1 << 12) +#define GEN6_THREADDISP_MASK_STACK_EXCEPTION (0x1 << 11) +#define GEN6_THREADDISP_SOFTWARE_EXCEPTION (0x1 << 7) +#define GEN6_THREADSCRATCH_ADDR__MASK 0xfffffc00 +#define GEN6_THREADSCRATCH_ADDR__SHIFT 10 +#define GEN6_THREADSCRATCH_ADDR__SHR 10 +#define GEN6_THREADSCRATCH_SPACE_PER_THREAD__MASK 0x0000000f +#define GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT 0 +#define GEN6_BASE_ADDR__MASK 0xfffff000 +#define GEN6_BASE_ADDR__SHIFT 12 +#define GEN6_BASE_ADDR__SHR 12 +#define GEN6_BASE_ADDR_MOCS__MASK 0x00000f00 +#define GEN6_BASE_ADDR_MOCS__SHIFT 8 +#define GEN6_BASE_ADDR_MODIFIED (0x1 << 0) +#define GEN6_STATE_BASE_ADDRESS__SIZE 10 + + +#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_MOCS__MASK 0x000000f0 +#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_MOCS__SHIFT 4 +#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_FORCE_WRITE_THRU (0x1 << 3) + + + + + + + + + +#define GEN6_STATE_SIP__SIZE 2 + + +#define GEN6_SIP_DW1_KERNEL_ADDR__MASK 0xfffffff0 +#define GEN6_SIP_DW1_KERNEL_ADDR__SHIFT 4 +#define GEN6_SIP_DW1_KERNEL_ADDR__SHR 4 + +#define GEN6_3DSTATE_VF_STATISTICS__SIZE 1 + +#define GEN6_VF_STATS_DW0_ENABLE (0x1 << 0) + +#define GEN6_PIPELINE_SELECT__SIZE 1 + +#define GEN6_PIPELINE_SELECT_DW0_SELECT__MASK 0x00000003 +#define GEN6_PIPELINE_SELECT_DW0_SELECT__SHIFT 0 +#define GEN6_PIPELINE_SELECT_DW0_SELECT_3D 0x0 +#define GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA 0x1 +#define GEN75_PIPELINE_SELECT_DW0_SELECT_GPGPU 0x2 + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE 4 + +#define GEN6_PTR_BINDING_TABLE_DW0_PS_CHANGED (0x1 << 12) +#define GEN6_PTR_BINDING_TABLE_DW0_GS_CHANGED (0x1 << 9) +#define GEN6_PTR_BINDING_TABLE_DW0_VS_CHANGED (0x1 << 8) + +#define GEN6_PTR_BINDING_TABLE_DW1_VS_ADDR__MASK 0xffffffe0 +#define GEN6_PTR_BINDING_TABLE_DW1_VS_ADDR__SHIFT 5 +#define GEN6_PTR_BINDING_TABLE_DW1_VS_ADDR__SHR 5 + +#define GEN6_PTR_BINDING_TABLE_DW2_GS_ADDR__MASK 0xffffffe0 +#define GEN6_PTR_BINDING_TABLE_DW2_GS_ADDR__SHIFT 5 +#define GEN6_PTR_BINDING_TABLE_DW2_GS_ADDR__SHR 5 + +#define GEN6_PTR_BINDING_TABLE_DW3_PS_ADDR__MASK 0xffffffe0 +#define GEN6_PTR_BINDING_TABLE_DW3_PS_ADDR__SHIFT 5 +#define GEN6_PTR_BINDING_TABLE_DW3_PS_ADDR__SHR 5 + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE 4 + +#define GEN6_PTR_SAMPLER_DW0_PS_CHANGED (0x1 << 12) +#define GEN6_PTR_SAMPLER_DW0_GS_CHANGED (0x1 << 9) +#define GEN6_PTR_SAMPLER_DW0_VS_CHANGED (0x1 << 8) + +#define GEN6_PTR_SAMPLER_DW1_VS_ADDR__MASK 0xffffffe0 +#define GEN6_PTR_SAMPLER_DW1_VS_ADDR__SHIFT 5 +#define GEN6_PTR_SAMPLER_DW1_VS_ADDR__SHR 5 + +#define GEN6_PTR_SAMPLER_DW2_GS_ADDR__MASK 0xffffffe0 +#define GEN6_PTR_SAMPLER_DW2_GS_ADDR__SHIFT 5 +#define GEN6_PTR_SAMPLER_DW2_GS_ADDR__SHR 5 + +#define GEN6_PTR_SAMPLER_DW3_PS_ADDR__MASK 0xffffffe0 +#define GEN6_PTR_SAMPLER_DW3_PS_ADDR__SHIFT 5 +#define GEN6_PTR_SAMPLER_DW3_PS_ADDR__SHR 5 + +#define GEN6_3DSTATE_URB__SIZE 3 + + +#define GEN6_URB_DW1_VS_ENTRY_SIZE__MASK 0x00ff0000 +#define GEN6_URB_DW1_VS_ENTRY_SIZE__SHIFT 16 +#define GEN6_URB_DW1_VS_ENTRY_COUNT__MASK 0x0000ffff +#define GEN6_URB_DW1_VS_ENTRY_COUNT__SHIFT 0 +#define GEN6_URB_DW1_VS_ENTRY_COUNT__ALIGN 4 + +#define GEN6_URB_DW2_GS_ENTRY_COUNT__MASK 0x0003ff00 +#define GEN6_URB_DW2_GS_ENTRY_COUNT__SHIFT 8 +#define GEN6_URB_DW2_GS_ENTRY_COUNT__ALIGN 4 +#define GEN6_URB_DW2_GS_ENTRY_SIZE__MASK 0x00000007 +#define GEN6_URB_DW2_GS_ENTRY_SIZE__SHIFT 0 + +#define GEN7_3DSTATE_URB_ANY__SIZE 2 + + +#define GEN7_URB_ANY_DW1_OFFSET__MASK 0x3e000000 +#define GEN7_URB_ANY_DW1_OFFSET__SHIFT 25 +#define GEN7_URB_ANY_DW1_ENTRY_SIZE__MASK 0x01ff0000 +#define GEN7_URB_ANY_DW1_ENTRY_SIZE__SHIFT 16 +#define GEN7_URB_ANY_DW1_ENTRY_COUNT__MASK 0x0000ffff +#define GEN7_URB_ANY_DW1_ENTRY_COUNT__SHIFT 0 + +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE 2 + + +#define GEN7_PCB_ALLOC_ANY_DW1_OFFSET__MASK 0x000f0000 +#define GEN7_PCB_ALLOC_ANY_DW1_OFFSET__SHIFT 16 +#define GEN7_PCB_ALLOC_ANY_DW1_SIZE__MASK 0x0000001f +#define GEN7_PCB_ALLOC_ANY_DW1_SIZE__SHIFT 0 + +#define GEN75_PCB_ALLOC_ANY_DW1_OFFSET__MASK 0x001f0000 +#define GEN75_PCB_ALLOC_ANY_DW1_OFFSET__SHIFT 16 +#define GEN75_PCB_ALLOC_ANY_DW1_SIZE__MASK 0x0000003f +#define GEN75_PCB_ALLOC_ANY_DW1_SIZE__SHIFT 0 + +#define GEN6_3DSTATE_VERTEX_BUFFERS__SIZE 133 + + +#define GEN6_VB_STATE_DW0_INDEX__MASK 0xfc000000 +#define GEN6_VB_STATE_DW0_INDEX__SHIFT 26 +#define GEN6_VB_STATE_DW0_ACCESS__MASK 0x00100000 +#define GEN6_VB_STATE_DW0_ACCESS__SHIFT 20 +#define GEN6_VB_STATE_DW0_ACCESS_VERTEXDATA (0x0 << 20) +#define GEN6_VB_STATE_DW0_ACCESS_INSTANCEDATA (0x1 << 20) +#define GEN6_VB_STATE_DW0_MOCS__MASK 0x000f0000 +#define GEN6_VB_STATE_DW0_MOCS__SHIFT 16 +#define GEN7_VB_STATE_DW0_ADDR_MODIFIED (0x1 << 14) +#define GEN6_VB_STATE_DW0_IS_NULL (0x1 << 13) +#define GEN6_VB_STATE_DW0_CACHE_INVALIDATE (0x1 << 12) +#define GEN6_VB_STATE_DW0_PITCH__MASK 0x00000fff +#define GEN6_VB_STATE_DW0_PITCH__SHIFT 0 + + + + +#define GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE 69 + + +#define GEN6_VE_STATE_DW0_VB_INDEX__MASK 0xfc000000 +#define GEN6_VE_STATE_DW0_VB_INDEX__SHIFT 26 +#define GEN6_VE_STATE_DW0_VALID (0x1 << 25) +#define GEN6_VE_STATE_DW0_FORMAT__MASK 0x01ff0000 +#define GEN6_VE_STATE_DW0_FORMAT__SHIFT 16 +#define GEN6_VE_STATE_DW0_EDGE_FLAG_ENABLE (0x1 << 15) +#define GEN6_VE_STATE_DW0_VB_OFFSET__MASK 0x000007ff +#define GEN6_VE_STATE_DW0_VB_OFFSET__SHIFT 0 +#define GEN75_VE_STATE_DW0_VB_OFFSET__MASK 0x00000fff +#define GEN75_VE_STATE_DW0_VB_OFFSET__SHIFT 0 + +#define GEN6_VE_STATE_DW1_COMP0__MASK 0x70000000 +#define GEN6_VE_STATE_DW1_COMP0__SHIFT 28 +#define GEN6_VE_STATE_DW1_COMP1__MASK 0x07000000 +#define GEN6_VE_STATE_DW1_COMP1__SHIFT 24 +#define GEN6_VE_STATE_DW1_COMP2__MASK 0x00700000 +#define GEN6_VE_STATE_DW1_COMP2__SHIFT 20 +#define GEN6_VE_STATE_DW1_COMP3__MASK 0x00070000 +#define GEN6_VE_STATE_DW1_COMP3__SHIFT 16 + +#define GEN6_3DSTATE_INDEX_BUFFER__SIZE 3 + +#define GEN6_IB_DW0_MOCS__MASK 0x0000f000 +#define GEN6_IB_DW0_MOCS__SHIFT 12 +#define GEN6_IB_DW0_CUT_INDEX_ENABLE (0x1 << 10) +#define GEN6_IB_DW0_FORMAT__MASK 0x00000300 +#define GEN6_IB_DW0_FORMAT__SHIFT 8 +#define GEN6_IB_DW0_FORMAT_BYTE (0x0 << 8) +#define GEN6_IB_DW0_FORMAT_WORD (0x1 << 8) +#define GEN6_IB_DW0_FORMAT_DWORD (0x2 << 8) + + + +#define GEN75_3DSTATE_VF__SIZE 2 + +#define GEN75_VF_DW0_CUT_INDEX_ENABLE (0x1 << 8) + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE 4 + +#define GEN6_PTR_VP_DW0_CC_CHANGED (0x1 << 12) +#define GEN6_PTR_VP_DW0_SF_CHANGED (0x1 << 11) +#define GEN6_PTR_VP_DW0_CLIP_CHANGED (0x1 << 10) + +#define GEN6_PTR_VP_DW1_CLIP_ADDR__MASK 0xffffffe0 +#define GEN6_PTR_VP_DW1_CLIP_ADDR__SHIFT 5 +#define GEN6_PTR_VP_DW1_CLIP_ADDR__SHR 5 + +#define GEN6_PTR_VP_DW2_SF_ADDR__MASK 0xffffffe0 +#define GEN6_PTR_VP_DW2_SF_ADDR__SHIFT 5 +#define GEN6_PTR_VP_DW2_SF_ADDR__SHR 5 + +#define GEN6_PTR_VP_DW3_CC_ADDR__MASK 0xffffffe0 +#define GEN6_PTR_VP_DW3_CC_ADDR__SHIFT 5 +#define GEN6_PTR_VP_DW3_CC_ADDR__SHR 5 + +#define GEN6_3DSTATE_CC_STATE_POINTERS__SIZE 4 + + +#define GEN6_PTR_CC_DW1_BLEND_CHANGED (0x1 << 0) +#define GEN6_PTR_CC_DW1_BLEND_ADDR__MASK 0xffffffc0 +#define GEN6_PTR_CC_DW1_BLEND_ADDR__SHIFT 6 +#define GEN6_PTR_CC_DW1_BLEND_ADDR__SHR 6 + +#define GEN6_PTR_CC_DW2_ZS_CHANGED (0x1 << 0) +#define GEN6_PTR_CC_DW2_ZS_ADDR__MASK 0xffffffc0 +#define GEN6_PTR_CC_DW2_ZS_ADDR__SHIFT 6 +#define GEN6_PTR_CC_DW2_ZS_ADDR__SHR 6 + +#define GEN6_PTR_CC_DW3_CC_CHANGED (0x1 << 0) +#define GEN6_PTR_CC_DW3_CC_ADDR__MASK 0xffffffc0 +#define GEN6_PTR_CC_DW3_CC_ADDR__SHIFT 6 +#define GEN6_PTR_CC_DW3_CC_ADDR__SHR 6 + +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE 2 + + +#define GEN6_PTR_SCISSOR_DW1_ADDR__MASK 0xffffffe0 +#define GEN6_PTR_SCISSOR_DW1_ADDR__SHIFT 5 +#define GEN6_PTR_SCISSOR_DW1_ADDR__SHR 5 + +#define GEN7_3DSTATE_POINTERS_ANY__SIZE 2 + + +#define GEN7_PTR_ANY_DW1_ADDR__MASK 0xffffffe0 +#define GEN7_PTR_ANY_DW1_ADDR__SHIFT 5 +#define GEN7_PTR_ANY_DW1_ADDR__SHR 5 + +#define GEN6_3DSTATE_VS__SIZE 6 + + +#define GEN6_VS_DW1_KERNEL_ADDR__MASK 0xffffffc0 +#define GEN6_VS_DW1_KERNEL_ADDR__SHIFT 6 +#define GEN6_VS_DW1_KERNEL_ADDR__SHR 6 + + + +#define GEN6_VS_DW4_URB_GRF_START__MASK 0x01f00000 +#define GEN6_VS_DW4_URB_GRF_START__SHIFT 20 +#define GEN6_VS_DW4_URB_READ_LEN__MASK 0x0001f800 +#define GEN6_VS_DW4_URB_READ_LEN__SHIFT 11 +#define GEN6_VS_DW4_URB_READ_OFFSET__MASK 0x000003f0 +#define GEN6_VS_DW4_URB_READ_OFFSET__SHIFT 4 + +#define GEN6_VS_DW5_MAX_THREADS__MASK 0xfe000000 +#define GEN6_VS_DW5_MAX_THREADS__SHIFT 25 +#define GEN75_VS_DW5_MAX_THREADS__MASK 0xff800000 +#define GEN75_VS_DW5_MAX_THREADS__SHIFT 23 +#define GEN6_VS_DW5_STATISTICS (0x1 << 10) +#define GEN6_VS_DW5_CACHE_DISABLE (0x1 << 1) +#define GEN6_VS_DW5_VS_ENABLE (0x1 << 0) + +#define GEN7_3DSTATE_HS__SIZE 7 + + +#define GEN7_HS_DW1_DISPATCH_MAX_THREADS__MASK 0x0000007f +#define GEN7_HS_DW1_DISPATCH_MAX_THREADS__SHIFT 0 +#define GEN75_HS_DW1_DISPATCH_MAX_THREADS__MASK 0x000000ff +#define GEN75_HS_DW1_DISPATCH_MAX_THREADS__SHIFT 0 + +#define GEN7_HS_DW2_HS_ENABLE (0x1 << 31) +#define GEN7_HS_DW2_STATISTICS (0x1 << 29) +#define GEN7_HS_DW2_INSTANCE_COUNT__MASK 0x0000000f +#define GEN7_HS_DW2_INSTANCE_COUNT__SHIFT 0 + +#define GEN7_HS_DW3_KERNEL_ADDR__MASK 0xffffffc0 +#define GEN7_HS_DW3_KERNEL_ADDR__SHIFT 6 +#define GEN7_HS_DW3_KERNEL_ADDR__SHR 6 + + +#define GEN7_HS_DW5_SPF (0x1 << 27) +#define GEN7_HS_DW5_VME (0x1 << 26) +#define GEN75_HS_DW5_ACCESS_UAV (0x1 << 25) +#define GEN7_HS_DW5_INCLUDE_VERTEX_HANDLES (0x1 << 24) +#define GEN7_HS_DW5_URB_GRF_START__MASK 0x00f80000 +#define GEN7_HS_DW5_URB_GRF_START__SHIFT 19 +#define GEN7_HS_DW5_URB_READ_LEN__MASK 0x0001f800 +#define GEN7_HS_DW5_URB_READ_LEN__SHIFT 11 +#define GEN7_HS_DW5_URB_READ_OFFSET__MASK 0x000003f0 +#define GEN7_HS_DW5_URB_READ_OFFSET__SHIFT 4 + +#define GEN7_HS_DW6_URB_SEMAPHORE_ADDR__MASK 0x00000fff +#define GEN7_HS_DW6_URB_SEMAPHORE_ADDR__SHIFT 0 +#define GEN7_HS_DW6_URB_SEMAPHORE_ADDR__SHR 6 +#define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__MASK 0x00001fff +#define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__SHIFT 0 +#define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__SHR 6 + +#define GEN7_3DSTATE_TE__SIZE 4 + + +#define GEN7_TE_DW1_PARTITIONING__MASK 0x00003000 +#define GEN7_TE_DW1_PARTITIONING__SHIFT 12 +#define GEN7_TE_DW1_PARTITIONING_INTEGER (0x0 << 12) +#define GEN7_TE_DW1_PARTITIONING_ODD_FRACTIONAL (0x1 << 12) +#define GEN7_TE_DW1_PARTITIONING_EVEN_FRACTIONAL (0x2 << 12) +#define GEN7_TE_DW1_OUTPUT_TOPO__MASK 0x00000300 +#define GEN7_TE_DW1_OUTPUT_TOPO__SHIFT 8 +#define GEN7_TE_DW1_OUTPUT_TOPO_POINT (0x0 << 8) +#define GEN7_TE_DW1_OUTPUT_TOPO_LINE (0x1 << 8) +#define GEN7_TE_DW1_OUTPUT_TOPO_TRI_CW (0x2 << 8) +#define GEN7_TE_DW1_OUTPUT_TOPO_TRI_CCW (0x3 << 8) +#define GEN7_TE_DW1_DOMAIN__MASK 0x00000030 +#define GEN7_TE_DW1_DOMAIN__SHIFT 4 +#define GEN7_TE_DW1_DOMAIN_QUAD (0x0 << 4) +#define GEN7_TE_DW1_DOMAIN_TRI (0x1 << 4) +#define GEN7_TE_DW1_DOMAIN_ISOLINE (0x2 << 4) +#define GEN7_TE_DW1_MODE__MASK 0x00000006 +#define GEN7_TE_DW1_MODE__SHIFT 1 +#define GEN7_TE_DW1_MODE_HW (0x0 << 1) +#define GEN7_TE_DW1_MODE_SW (0x1 << 1) +#define GEN7_TE_DW1_TE_ENABLE (0x1 << 0) + + + +#define GEN7_3DSTATE_DS__SIZE 6 + + +#define GEN7_DS_DW1_KERNEL_ADDR__MASK 0xffffffc0 +#define GEN7_DS_DW1_KERNEL_ADDR__SHIFT 6 +#define GEN7_DS_DW1_KERNEL_ADDR__SHR 6 + + + +#define GEN7_DS_DW4_URB_GRF_START__MASK 0x01f00000 +#define GEN7_DS_DW4_URB_GRF_START__SHIFT 20 +#define GEN7_DS_DW4_URB_READ_LEN__MASK 0x0003f800 +#define GEN7_DS_DW4_URB_READ_LEN__SHIFT 11 +#define GEN7_DS_DW4_URB_READ_OFFSET__MASK 0x000003f0 +#define GEN7_DS_DW4_URB_READ_OFFSET__SHIFT 4 + +#define GEN7_DS_DW5_MAX_THREADS__MASK 0xfe000000 +#define GEN7_DS_DW5_MAX_THREADS__SHIFT 25 +#define GEN75_DS_DW5_MAX_THREADS__MASK 0x3fe00000 +#define GEN75_DS_DW5_MAX_THREADS__SHIFT 21 +#define GEN7_DS_DW5_STATISTICS (0x1 << 10) +#define GEN7_DS_DW5_COMPUTE_W (0x1 << 2) +#define GEN7_DS_DW5_CACHE_DISABLE (0x1 << 1) +#define GEN7_DS_DW5_DS_ENABLE (0x1 << 0) + +#define GEN6_3DSTATE_GS__SIZE 7 + + +#define GEN6_GS_DW1_KERNEL_ADDR__MASK 0xffffffc0 +#define GEN6_GS_DW1_KERNEL_ADDR__SHIFT 6 +#define GEN6_GS_DW1_KERNEL_ADDR__SHR 6 + + + +#define GEN6_GS_DW4_URB_READ_LEN__MASK 0x0001f800 +#define GEN6_GS_DW4_URB_READ_LEN__SHIFT 11 +#define GEN6_GS_DW4_URB_READ_OFFSET__MASK 0x000003f0 +#define GEN6_GS_DW4_URB_READ_OFFSET__SHIFT 4 +#define GEN6_GS_DW4_URB_GRF_START__MASK 0x0000000f +#define GEN6_GS_DW4_URB_GRF_START__SHIFT 0 + +#define GEN6_GS_DW5_MAX_THREADS__MASK 0xfe000000 +#define GEN6_GS_DW5_MAX_THREADS__SHIFT 25 +#define GEN6_GS_DW5_STATISTICS (0x1 << 10) +#define GEN6_GS_DW5_SO_STATISTICS (0x1 << 9) +#define GEN6_GS_DW5_RENDER_ENABLE (0x1 << 8) + +#define GEN6_GS_DW6_REORDER_ENABLE (0x1 << 30) +#define GEN6_GS_DW6_DISCARD_ADJACENCY (0x1 << 29) +#define GEN6_GS_DW6_SVBI_PAYLOAD_ENABLE (0x1 << 28) +#define GEN6_GS_DW6_SVBI_POST_INC_ENABLE (0x1 << 27) +#define GEN6_GS_DW6_SVBI_POST_INC_VAL__MASK 0x03ff0000 +#define GEN6_GS_DW6_SVBI_POST_INC_VAL__SHIFT 16 +#define GEN6_GS_DW6_GS_ENABLE (0x1 << 15) + + + +#define GEN7_GS_DW1_KERNEL_ADDR__MASK 0xffffffc0 +#define GEN7_GS_DW1_KERNEL_ADDR__SHIFT 6 +#define GEN7_GS_DW1_KERNEL_ADDR__SHR 6 + + + +#define GEN7_GS_DW4_OUTPUT_SIZE__MASK 0x1f800000 +#define GEN7_GS_DW4_OUTPUT_SIZE__SHIFT 23 +#define GEN7_GS_DW4_OUTPUT_TOPO__MASK 0x007e0000 +#define GEN7_GS_DW4_OUTPUT_TOPO__SHIFT 17 +#define GEN7_GS_DW4_URB_READ_LEN__MASK 0x0001f800 +#define GEN7_GS_DW4_URB_READ_LEN__SHIFT 11 +#define GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES (0x1 << 10) +#define GEN7_GS_DW4_URB_READ_OFFSET__MASK 0x000003f0 +#define GEN7_GS_DW4_URB_READ_OFFSET__SHIFT 4 +#define GEN7_GS_DW4_URB_GRF_START__MASK 0x0000000f +#define GEN7_GS_DW4_URB_GRF_START__SHIFT 0 + +#define GEN7_GS_DW5_MAX_THREADS__MASK 0xfe000000 +#define GEN7_GS_DW5_MAX_THREADS__SHIFT 25 +#define GEN7_GS_DW5_GSCTRL__MASK 0x01000000 +#define GEN7_GS_DW5_GSCTRL__SHIFT 24 +#define GEN7_GS_DW5_GSCTRL_CUT (0x0 << 24) +#define GEN7_GS_DW5_GSCTRL_SID (0x1 << 24) +#define GEN75_GS_DW5_MAX_THREADS__MASK 0xff000000 +#define GEN75_GS_DW5_MAX_THREADS__SHIFT 24 +#define GEN7_GS_DW5_CONTROL_DATA_HEADER_SIZE__MASK 0x00f00000 +#define GEN7_GS_DW5_CONTROL_DATA_HEADER_SIZE__SHIFT 20 +#define GEN7_GS_DW5_INSTANCE_CONTROL__MASK 0x000f8000 +#define GEN7_GS_DW5_INSTANCE_CONTROL__SHIFT 15 +#define GEN7_GS_DW5_DEFAULT_STREAM_ID__MASK 0x00006000 +#define GEN7_GS_DW5_DEFAULT_STREAM_ID__SHIFT 13 +#define GEN7_GS_DW5_DISPATCH_MODE__MASK 0x00001800 +#define GEN7_GS_DW5_DISPATCH_MODE__SHIFT 11 +#define GEN7_GS_DW5_DISPATCH_MODE_SINGLE (0x0 << 11) +#define GEN7_GS_DW5_DISPATCH_MODE_DUAL_INSTANCE (0x1 << 11) +#define GEN7_GS_DW5_DISPATCH_MODE_DUAL_OBJECT (0x2 << 11) +#define GEN7_GS_DW5_STATISTICS (0x1 << 10) +#define GEN7_GS_DW5_INVOCATION_INCR__MASK 0x000003e0 +#define GEN7_GS_DW5_INVOCATION_INCR__SHIFT 5 +#define GEN7_GS_DW5_INCLUDE_PRIMITIVE_ID (0x1 << 4) +#define GEN7_GS_DW5_HINT (0x1 << 3) +#define GEN7_GS_DW5_REORDER_ENABLE (0x1 << 2) +#define GEN75_GS_DW5_REORDER__MASK 0x00000004 +#define GEN75_GS_DW5_REORDER__SHIFT 2 +#define GEN75_GS_DW5_REORDER_LEADING (0x0 << 2) +#define GEN75_GS_DW5_REORDER_TRAILING (0x1 << 2) +#define GEN7_GS_DW5_DISCARD_ADJACENCY (0x1 << 1) +#define GEN7_GS_DW5_GS_ENABLE (0x1 << 0) + +#define GEN75_GS_DW6_GSCTRL__MASK 0x80000000 +#define GEN75_GS_DW6_GSCTRL__SHIFT 31 +#define GEN75_GS_DW6_GSCTRL_CUT (0x0 << 31) +#define GEN75_GS_DW6_GSCTRL_SID (0x1 << 31) +#define GEN7_GS_DW6_URB_SEMAPHORE_ADDR__MASK 0x00000fff +#define GEN7_GS_DW6_URB_SEMAPHORE_ADDR__SHIFT 0 +#define GEN7_GS_DW6_URB_SEMAPHORE_ADDR__SHR 6 +#define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__MASK 0x00001fff +#define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__SHIFT 0 +#define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__SHR 6 + +#define GEN7_3DSTATE_STREAMOUT__SIZE 3 + + +#define GEN7_SO_DW1_SO_ENABLE (0x1 << 31) +#define GEN7_SO_DW1_RENDER_DISABLE (0x1 << 30) +#define GEN7_SO_DW1_RENDER_STREAM_SELECT__MASK 0x18000000 +#define GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT 27 +#define GEN7_SO_DW1_REORDER__MASK 0x04000000 +#define GEN7_SO_DW1_REORDER__SHIFT 26 +#define GEN7_SO_DW1_REORDER_LEADING (0x0 << 26) +#define GEN7_SO_DW1_REORDER_TRAILING (0x1 << 26) +#define GEN7_SO_DW1_STATISTICS (0x1 << 25) +#define GEN7_SO_DW1_BUFFER_ENABLES__MASK 0x00000f00 +#define GEN7_SO_DW1_BUFFER_ENABLES__SHIFT 8 + +#define GEN7_SO_DW2_STREAM3_READ_OFFSET__MASK 0x20000000 +#define GEN7_SO_DW2_STREAM3_READ_OFFSET__SHIFT 29 +#define GEN7_SO_DW2_STREAM3_READ_LEN__MASK 0x1f000000 +#define GEN7_SO_DW2_STREAM3_READ_LEN__SHIFT 24 +#define GEN7_SO_DW2_STREAM2_READ_OFFSET__MASK 0x00200000 +#define GEN7_SO_DW2_STREAM2_READ_OFFSET__SHIFT 21 +#define GEN7_SO_DW2_STREAM2_READ_LEN__MASK 0x001f0000 +#define GEN7_SO_DW2_STREAM2_READ_LEN__SHIFT 16 +#define GEN7_SO_DW2_STREAM1_READ_OFFSET__MASK 0x00002000 +#define GEN7_SO_DW2_STREAM1_READ_OFFSET__SHIFT 13 +#define GEN7_SO_DW2_STREAM1_READ_LEN__MASK 0x00001f00 +#define GEN7_SO_DW2_STREAM1_READ_LEN__SHIFT 8 +#define GEN7_SO_DW2_STREAM0_READ_OFFSET__MASK 0x00000020 +#define GEN7_SO_DW2_STREAM0_READ_OFFSET__SHIFT 5 +#define GEN7_SO_DW2_STREAM0_READ_LEN__MASK 0x0000001f +#define GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT 0 + +#define GEN7_3DSTATE_SO_DECL_LIST__SIZE 259 + + +#define GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__MASK 0x0000f000 +#define GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__SHIFT 12 +#define GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__MASK 0x00000f00 +#define GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__SHIFT 8 +#define GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__MASK 0x000000f0 +#define GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__SHIFT 4 +#define GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__MASK 0x0000000f +#define GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__SHIFT 0 + +#define GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__MASK 0xff000000 +#define GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__SHIFT 24 +#define GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__MASK 0x00ff0000 +#define GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__SHIFT 16 +#define GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__MASK 0x0000ff00 +#define GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__SHIFT 8 +#define GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__MASK 0x000000ff +#define GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__SHIFT 0 + +#define GEN7_SO_DECL_HIGH__MASK 0xffff0000 +#define GEN7_SO_DECL_HIGH__SHIFT 16 +#define GEN7_SO_DECL_OUTPUT_SLOT__MASK 0x00003000 +#define GEN7_SO_DECL_OUTPUT_SLOT__SHIFT 12 +#define GEN7_SO_DECL_HOLE_FLAG (0x1 << 11) +#define GEN7_SO_DECL_REG_INDEX__MASK 0x000003f0 +#define GEN7_SO_DECL_REG_INDEX__SHIFT 4 +#define GEN7_SO_DECL_COMPONENT_MASK__MASK 0x0000000f +#define GEN7_SO_DECL_COMPONENT_MASK__SHIFT 0 + +#define GEN7_3DSTATE_SO_BUFFER__SIZE 4 + + +#define GEN7_SO_BUF_DW1_INDEX__MASK 0x60000000 +#define GEN7_SO_BUF_DW1_INDEX__SHIFT 29 +#define GEN7_SO_BUF_DW1_MOCS__MASK 0x1e000000 +#define GEN7_SO_BUF_DW1_MOCS__SHIFT 25 +#define GEN7_SO_BUF_DW1_PITCH__MASK 0x00000fff +#define GEN7_SO_BUF_DW1_PITCH__SHIFT 0 + +#define GEN7_SO_BUF_DW2_START_ADDR__MASK 0xfffffffc +#define GEN7_SO_BUF_DW2_START_ADDR__SHIFT 2 +#define GEN7_SO_BUF_DW2_START_ADDR__SHR 2 + +#define GEN7_SO_BUF_DW3_END_ADDR__MASK 0xfffffffc +#define GEN7_SO_BUF_DW3_END_ADDR__SHIFT 2 +#define GEN7_SO_BUF_DW3_END_ADDR__SHR 2 + +#define GEN6_3DSTATE_CLIP__SIZE 4 + + +#define GEN7_CLIP_DW1_FRONTWINDING__MASK 0x00100000 +#define GEN7_CLIP_DW1_FRONTWINDING__SHIFT 20 +#define GEN7_CLIP_DW1_FRONTWINDING_CW (0x0 << 20) +#define GEN7_CLIP_DW1_FRONTWINDING_CCW (0x1 << 20) +#define GEN7_CLIP_DW1_SUBPIXEL__MASK 0x00080000 +#define GEN7_CLIP_DW1_SUBPIXEL__SHIFT 19 +#define GEN7_CLIP_DW1_SUBPIXEL_8BITS (0x0 << 19) +#define GEN7_CLIP_DW1_SUBPIXEL_4BITS (0x1 << 19) +#define GEN7_CLIP_DW1_EARLY_CULL_ENABLE (0x1 << 18) +#define GEN7_CLIP_DW1_CULLMODE__MASK 0x00030000 +#define GEN7_CLIP_DW1_CULLMODE__SHIFT 16 +#define GEN7_CLIP_DW1_CULLMODE_BOTH (0x0 << 16) +#define GEN7_CLIP_DW1_CULLMODE_NONE (0x1 << 16) +#define GEN7_CLIP_DW1_CULLMODE_FRONT (0x2 << 16) +#define GEN7_CLIP_DW1_CULLMODE_BACK (0x3 << 16) +#define GEN6_CLIP_DW1_STATISTICS (0x1 << 10) +#define GEN6_CLIP_DW1_UCP_CULL_ENABLES__MASK 0x000000ff +#define GEN6_CLIP_DW1_UCP_CULL_ENABLES__SHIFT 0 + +#define GEN6_CLIP_DW2_CLIP_ENABLE (0x1 << 31) +#define GEN6_CLIP_DW2_APIMODE__MASK 0x40000000 +#define GEN6_CLIP_DW2_APIMODE__SHIFT 30 +#define GEN6_CLIP_DW2_APIMODE_OGL (0x0 << 30) +#define GEN6_CLIP_DW2_APIMODE_D3D (0x1 << 30) +#define GEN6_CLIP_DW2_XY_TEST_ENABLE (0x1 << 28) +#define GEN6_CLIP_DW2_Z_TEST_ENABLE (0x1 << 27) +#define GEN6_CLIP_DW2_GB_TEST_ENABLE (0x1 << 26) +#define GEN6_CLIP_DW2_UCP_CLIP_ENABLES__MASK 0x00ff0000 +#define GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT 16 +#define GEN6_CLIP_DW2_CLIPMODE__MASK 0x0000e000 +#define GEN6_CLIP_DW2_CLIPMODE__SHIFT 13 +#define GEN6_CLIP_DW2_CLIPMODE_NORMAL (0x0 << 13) +#define GEN6_CLIP_DW2_CLIPMODE_REJECT_ALL (0x3 << 13) +#define GEN6_CLIP_DW2_CLIPMODE_ACCEPT_ALL (0x4 << 13) +#define GEN6_CLIP_DW2_PERSPECTIVE_DIVIDE_DISABLE (0x1 << 9) +#define GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE (0x1 << 8) +#define GEN6_CLIP_DW2_TRI_PROVOKE__MASK 0x00000030 +#define GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT 4 +#define GEN6_CLIP_DW2_LINE_PROVOKE__MASK 0x0000000c +#define GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT 2 +#define GEN6_CLIP_DW2_TRIFAN_PROVOKE__MASK 0x00000003 +#define GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT 0 + +#define GEN6_CLIP_DW3_MIN_POINT_WIDTH__MASK 0x0ffe0000 +#define GEN6_CLIP_DW3_MIN_POINT_WIDTH__SHIFT 17 +#define GEN6_CLIP_DW3_MIN_POINT_WIDTH__RADIX 3 +#define GEN6_CLIP_DW3_MAX_POINT_WIDTH__MASK 0x0001ffc0 +#define GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT 6 +#define GEN6_CLIP_DW3_MAX_POINT_WIDTH__RADIX 3 +#define GEN6_CLIP_DW3_RTAINDEX_FORCED_ZERO (0x1 << 5) +#define GEN6_CLIP_DW3_MAX_VPINDEX__MASK 0x0000000f +#define GEN6_CLIP_DW3_MAX_VPINDEX__SHIFT 0 + +#define GEN6_3DSTATE_SFBODY__SIZE 6 + +#define GEN7_SF_DW1_DEPTH_FORMAT__MASK 0x00007000 +#define GEN7_SF_DW1_DEPTH_FORMAT__SHIFT 12 +#define GEN7_SF_DW1_LEGACY_DEPTH_OFFSET (0x1 << 11) +#define GEN7_SF_DW1_STATISTICS (0x1 << 10) +#define GEN7_SF_DW1_DEPTH_OFFSET_SOLID (0x1 << 9) +#define GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME (0x1 << 8) +#define GEN7_SF_DW1_DEPTH_OFFSET_POINT (0x1 << 7) +#define GEN7_SF_DW1_FRONTFACE__MASK 0x00000060 +#define GEN7_SF_DW1_FRONTFACE__SHIFT 5 +#define GEN7_SF_DW1_FRONTFACE_SOLID (0x0 << 5) +#define GEN7_SF_DW1_FRONTFACE_WIREFRAME (0x1 << 5) +#define GEN7_SF_DW1_FRONTFACE_POINT (0x2 << 5) +#define GEN7_SF_DW1_BACKFACE__MASK 0x00000018 +#define GEN7_SF_DW1_BACKFACE__SHIFT 3 +#define GEN7_SF_DW1_BACKFACE_SOLID (0x0 << 3) +#define GEN7_SF_DW1_BACKFACE_WIREFRAME (0x1 << 3) +#define GEN7_SF_DW1_BACKFACE_POINT (0x2 << 3) +#define GEN7_SF_DW1_VIEWPORT_ENABLE (0x1 << 1) +#define GEN7_SF_DW1_FRONTWINDING__MASK 0x00000001 +#define GEN7_SF_DW1_FRONTWINDING__SHIFT 0 +#define GEN7_SF_DW1_FRONTWINDING_CW 0x0 +#define GEN7_SF_DW1_FRONTWINDING_CCW 0x1 + +#define GEN7_SF_DW2_AA_LINE_ENABLE (0x1 << 31) +#define GEN7_SF_DW2_CULLMODE__MASK 0x60000000 +#define GEN7_SF_DW2_CULLMODE__SHIFT 29 +#define GEN7_SF_DW2_CULLMODE_BOTH (0x0 << 29) +#define GEN7_SF_DW2_CULLMODE_NONE (0x1 << 29) +#define GEN7_SF_DW2_CULLMODE_FRONT (0x2 << 29) +#define GEN7_SF_DW2_CULLMODE_BACK (0x3 << 29) +#define GEN7_SF_DW2_LINE_WIDTH__MASK 0x0ffc0000 +#define GEN7_SF_DW2_LINE_WIDTH__SHIFT 18 +#define GEN7_SF_DW2_LINE_WIDTH__RADIX 7 +#define GEN7_SF_DW2_AA_LINE_CAP__MASK 0x00030000 +#define GEN7_SF_DW2_AA_LINE_CAP__SHIFT 16 +#define GEN7_SF_DW2_AA_LINE_CAP_0_5 (0x0 << 16) +#define GEN7_SF_DW2_AA_LINE_CAP_1_0 (0x1 << 16) +#define GEN7_SF_DW2_AA_LINE_CAP_2_0 (0x2 << 16) +#define GEN7_SF_DW2_AA_LINE_CAP_4_0 (0x3 << 16) +#define GEN75_SF_DW2_LINE_STIPPLE_ENABLE (0x1 << 14) +#define GEN7_SF_DW2_SCISSOR_ENABLE (0x1 << 11) +#define GEN7_SF_DW2_MSRASTMODE__MASK 0x00000300 +#define GEN7_SF_DW2_MSRASTMODE__SHIFT 8 +#define GEN7_SF_DW2_MSRASTMODE_OFF_PIXEL (0x0 << 8) +#define GEN7_SF_DW2_MSRASTMODE_OFF_PATTERN (0x1 << 8) +#define GEN7_SF_DW2_MSRASTMODE_ON_PIXEL (0x2 << 8) +#define GEN7_SF_DW2_MSRASTMODE_ON_PATTERN (0x3 << 8) + +#define GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE (0x1 << 31) +#define GEN7_SF_DW3_TRI_PROVOKE__MASK 0x60000000 +#define GEN7_SF_DW3_TRI_PROVOKE__SHIFT 29 +#define GEN7_SF_DW3_LINE_PROVOKE__MASK 0x18000000 +#define GEN7_SF_DW3_LINE_PROVOKE__SHIFT 27 +#define GEN7_SF_DW3_TRIFAN_PROVOKE__MASK 0x06000000 +#define GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT 25 +#define GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE (0x1 << 14) +#define GEN7_SF_DW3_SUBPIXEL__MASK 0x00001000 +#define GEN7_SF_DW3_SUBPIXEL__SHIFT 12 +#define GEN7_SF_DW3_SUBPIXEL_8BITS (0x0 << 12) +#define GEN7_SF_DW3_SUBPIXEL_4BITS (0x1 << 12) +#define GEN7_SF_DW3_USE_POINT_WIDTH (0x1 << 11) +#define GEN7_SF_DW3_POINT_WIDTH__MASK 0x000007ff +#define GEN7_SF_DW3_POINT_WIDTH__SHIFT 0 +#define GEN7_SF_DW3_POINT_WIDTH__RADIX 3 + + + + +#define GEN6_3DSTATE_SBEBODY__SIZE 13 + +#define GEN7_SBE_DW1_ATTR_SWIZZLE__MASK 0x10000000 +#define GEN7_SBE_DW1_ATTR_SWIZZLE__SHIFT 28 +#define GEN7_SBE_DW1_ATTR_SWIZZLE_0_15 (0x0 << 28) +#define GEN7_SBE_DW1_ATTR_SWIZZLE_16_31 (0x1 << 28) +#define GEN7_SBE_DW1_ATTR_COUNT__MASK 0x0fc00000 +#define GEN7_SBE_DW1_ATTR_COUNT__SHIFT 22 +#define GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE (0x1 << 21) +#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD__MASK 0x00100000 +#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD__SHIFT 20 +#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT (0x0 << 20) +#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT (0x1 << 20) +#define GEN7_SBE_DW1_URB_READ_LEN__MASK 0x0000f800 +#define GEN7_SBE_DW1_URB_READ_LEN__SHIFT 11 +#define GEN7_SBE_DW1_URB_READ_OFFSET__MASK 0x000003f0 +#define GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT 4 + +#define GEN7_SBE_ATTR_HIGH__MASK 0xffff0000 +#define GEN7_SBE_ATTR_HIGH__SHIFT 16 +#define GEN7_SBE_ATTR_OVERRIDE_W (0x1 << 15) +#define GEN7_SBE_ATTR_OVERRIDE_Z (0x1 << 14) +#define GEN7_SBE_ATTR_OVERRIDE_Y (0x1 << 13) +#define GEN7_SBE_ATTR_OVERRIDE_X (0x1 << 12) +#define GEN7_SBE_ATTR_CONST__MASK 0x00000600 +#define GEN7_SBE_ATTR_CONST__SHIFT 9 +#define GEN7_SBE_ATTR_CONST_0000 (0x0 << 9) +#define GEN7_SBE_ATTR_CONST_0001_FLOAT (0x1 << 9) +#define GEN7_SBE_ATTR_CONST_1111_FLOAT (0x2 << 9) +#define GEN7_SBE_ATTR_CONST_PRIM_ID (0x3 << 9) +#define GEN7_SBE_ATTR_INPUTATTR__MASK 0x000000c0 +#define GEN7_SBE_ATTR_INPUTATTR__SHIFT 6 +#define GEN7_SBE_ATTR_INPUTATTR_NORMAL (0x0 << 6) +#define GEN7_SBE_ATTR_INPUTATTR_FACING (0x1 << 6) +#define GEN7_SBE_ATTR_INPUTATTR_W (0x2 << 6) +#define GEN7_SBE_ATTR_INPUTATTR_FACING_W (0x3 << 6) +#define GEN7_SBE_ATTR_URB_ENTRY_OFFSET__MASK 0x0000001f +#define GEN7_SBE_ATTR_URB_ENTRY_OFFSET__SHIFT 0 + + + + +#define GEN6_3DSTATE_SF__SIZE 20 + + + + +#define GEN7_3DSTATE_SBE__SIZE 14 + + + +#define GEN6_3DSTATE_WM__SIZE 9 + + +#define GEN6_WM_DW1_KERNEL0_ADDR__MASK 0xffffffc0 +#define GEN6_WM_DW1_KERNEL0_ADDR__SHIFT 6 +#define GEN6_WM_DW1_KERNEL0_ADDR__SHR 6 + + + +#define GEN6_WM_DW4_STATISTICS (0x1 << 31) +#define GEN6_WM_DW4_DEPTH_CLEAR (0x1 << 30) +#define GEN6_WM_DW4_DEPTH_RESOLVE (0x1 << 28) +#define GEN6_WM_DW4_HIZ_RESOLVE (0x1 << 27) +#define GEN6_WM_DW4_URB_GRF_START0__MASK 0x007f0000 +#define GEN6_WM_DW4_URB_GRF_START0__SHIFT 16 +#define GEN6_WM_DW4_URB_GRF_START1__MASK 0x00007f00 +#define GEN6_WM_DW4_URB_GRF_START1__SHIFT 8 +#define GEN6_WM_DW4_URB_GRF_START2__MASK 0x0000007f +#define GEN6_WM_DW4_URB_GRF_START2__SHIFT 0 + +#define GEN6_WM_DW5_MAX_THREADS__MASK 0xfe000000 +#define GEN6_WM_DW5_MAX_THREADS__SHIFT 25 +#define GEN6_WM_DW5_LEGACY_LINE_RAST (0x1 << 23) +#define GEN6_WM_DW5_PS_KILL (0x1 << 22) +#define GEN6_WM_DW5_PS_COMPUTE_DEPTH (0x1 << 21) +#define GEN6_WM_DW5_PS_USE_DEPTH (0x1 << 20) +#define GEN6_WM_DW5_PS_ENABLE (0x1 << 19) +#define GEN6_WM_DW5_AA_LINE_CAP__MASK 0x00030000 +#define GEN6_WM_DW5_AA_LINE_CAP__SHIFT 16 +#define GEN6_WM_DW5_AA_LINE_CAP_0_5 (0x0 << 16) +#define GEN6_WM_DW5_AA_LINE_CAP_1_0 (0x1 << 16) +#define GEN6_WM_DW5_AA_LINE_CAP_2_0 (0x2 << 16) +#define GEN6_WM_DW5_AA_LINE_CAP_4_0 (0x3 << 16) +#define GEN6_WM_DW5_AA_LINE_WIDTH__MASK 0x0000c000 +#define GEN6_WM_DW5_AA_LINE_WIDTH__SHIFT 14 +#define GEN6_WM_DW5_AA_LINE_WIDTH_0_5 (0x0 << 14) +#define GEN6_WM_DW5_AA_LINE_WIDTH_1_0 (0x1 << 14) +#define GEN6_WM_DW5_AA_LINE_WIDTH_2_0 (0x2 << 14) +#define GEN6_WM_DW5_AA_LINE_WIDTH_4_0 (0x3 << 14) +#define GEN6_WM_DW5_POLY_STIPPLE_ENABLE (0x1 << 13) +#define GEN6_WM_DW5_LINE_STIPPLE_ENABLE (0x1 << 11) +#define GEN6_WM_DW5_PS_COMPUTE_OMASK (0x1 << 9) +#define GEN6_WM_DW5_PS_USE_W (0x1 << 8) +#define GEN6_WM_DW5_DUAL_SOURCE_BLEND (0x1 << 7) +#define GEN6_WM_DW5_32_PIXEL_DISPATCH (0x1 << 2) +#define GEN6_WM_DW5_16_PIXEL_DISPATCH (0x1 << 1) +#define GEN6_WM_DW5_8_PIXEL_DISPATCH (0x1 << 0) + +#define GEN6_WM_DW6_SF_ATTR_COUNT__MASK 0x03f00000 +#define GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT 20 +#define GEN6_WM_DW6_POSOFFSET__MASK 0x000c0000 +#define GEN6_WM_DW6_POSOFFSET__SHIFT 18 +#define GEN6_WM_DW6_POSOFFSET_NONE (0x0 << 18) +#define GEN6_WM_DW6_POSOFFSET_CENTROID (0x2 << 18) +#define GEN6_WM_DW6_POSOFFSET_SAMPLE (0x3 << 18) +#define GEN6_WM_DW6_ZW_INTERP__MASK 0x00030000 +#define GEN6_WM_DW6_ZW_INTERP__SHIFT 16 +#define GEN6_WM_DW6_ZW_INTERP_PIXEL (0x0 << 16) +#define GEN6_WM_DW6_ZW_INTERP_CENTROID (0x2 << 16) +#define GEN6_WM_DW6_ZW_INTERP_SAMPLE (0x3 << 16) +#define GEN6_WM_DW6_BARYCENTRIC_INTERP__MASK 0x0000fc00 +#define GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT 10 +#define GEN6_WM_DW6_POINT_RASTRULE__MASK 0x00000200 +#define GEN6_WM_DW6_POINT_RASTRULE__SHIFT 9 +#define GEN6_WM_DW6_POINT_RASTRULE_UPPER_LEFT (0x0 << 9) +#define GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT (0x1 << 9) +#define GEN6_WM_DW6_MSRASTMODE__MASK 0x00000006 +#define GEN6_WM_DW6_MSRASTMODE__SHIFT 1 +#define GEN6_WM_DW6_MSRASTMODE_OFF_PIXEL (0x0 << 1) +#define GEN6_WM_DW6_MSRASTMODE_OFF_PATTERN (0x1 << 1) +#define GEN6_WM_DW6_MSRASTMODE_ON_PIXEL (0x2 << 1) +#define GEN6_WM_DW6_MSRASTMODE_ON_PATTERN (0x3 << 1) +#define GEN6_WM_DW6_MSDISPMODE__MASK 0x00000001 +#define GEN6_WM_DW6_MSDISPMODE__SHIFT 0 +#define GEN6_WM_DW6_MSDISPMODE_PERSAMPLE 0x0 +#define GEN6_WM_DW6_MSDISPMODE_PERPIXEL 0x1 + +#define GEN6_WM_DW7_KERNEL1_ADDR__MASK 0xffffffc0 +#define GEN6_WM_DW7_KERNEL1_ADDR__SHIFT 6 +#define GEN6_WM_DW7_KERNEL1_ADDR__SHR 6 + +#define GEN6_WM_DW8_KERNEL2_ADDR__MASK 0xffffffc0 +#define GEN6_WM_DW8_KERNEL2_ADDR__SHIFT 6 +#define GEN6_WM_DW8_KERNEL2_ADDR__SHR 6 + + +#define GEN7_WM_DW1_STATISTICS (0x1 << 31) +#define GEN7_WM_DW1_DEPTH_CLEAR (0x1 << 30) +#define GEN7_WM_DW1_PS_ENABLE (0x1 << 29) +#define GEN7_WM_DW1_DEPTH_RESOLVE (0x1 << 28) +#define GEN7_WM_DW1_HIZ_RESOLVE (0x1 << 27) +#define GEN7_WM_DW1_LEGACY_LINE_RAST (0x1 << 26) +#define GEN7_WM_DW1_PS_KILL (0x1 << 25) +#define GEN7_WM_DW1_PSCDEPTH__MASK 0x01800000 +#define GEN7_WM_DW1_PSCDEPTH__SHIFT 23 +#define GEN7_WM_DW1_PSCDEPTH_OFF (0x0 << 23) +#define GEN7_WM_DW1_PSCDEPTH_ON (0x1 << 23) +#define GEN7_WM_DW1_PSCDEPTH_ON_GE (0x2 << 23) +#define GEN7_WM_DW1_PSCDEPTH_ON_LE (0x3 << 23) +#define GEN7_WM_DW1_EDSC__MASK 0x00600000 +#define GEN7_WM_DW1_EDSC__SHIFT 21 +#define GEN7_WM_DW1_EDSC_NORMAL (0x0 << 21) +#define GEN7_WM_DW1_EDSC_PSEXEC (0x1 << 21) +#define GEN7_WM_DW1_EDSC_PREPS (0x2 << 21) +#define GEN7_WM_DW1_PS_USE_DEPTH (0x1 << 20) +#define GEN7_WM_DW1_PS_USE_W (0x1 << 19) +#define GEN7_WM_DW1_ZW_INTERP__MASK 0x00060000 +#define GEN7_WM_DW1_ZW_INTERP__SHIFT 17 +#define GEN7_WM_DW1_ZW_INTERP_PIXEL (0x0 << 17) +#define GEN7_WM_DW1_ZW_INTERP_CENTROID (0x2 << 17) +#define GEN7_WM_DW1_ZW_INTERP_SAMPLE (0x3 << 17) +#define GEN7_WM_DW1_BARYCENTRIC_INTERP__MASK 0x0001f800 +#define GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT 11 +#define GEN7_WM_DW1_PS_USE_COVERAGE (0x1 << 10) +#define GEN7_WM_DW1_AA_LINE_CAP__MASK 0x00000300 +#define GEN7_WM_DW1_AA_LINE_CAP__SHIFT 8 +#define GEN7_WM_DW1_AA_LINE_CAP_0_5 (0x0 << 8) +#define GEN7_WM_DW1_AA_LINE_CAP_1_0 (0x1 << 8) +#define GEN7_WM_DW1_AA_LINE_CAP_2_0 (0x2 << 8) +#define GEN7_WM_DW1_AA_LINE_CAP_4_0 (0x3 << 8) +#define GEN7_WM_DW1_AA_LINE_WIDTH__MASK 0x000000c0 +#define GEN7_WM_DW1_AA_LINE_WIDTH__SHIFT 6 +#define GEN7_WM_DW1_AA_LINE_WIDTH_0_5 (0x0 << 6) +#define GEN7_WM_DW1_AA_LINE_WIDTH_1_0 (0x1 << 6) +#define GEN7_WM_DW1_AA_LINE_WIDTH_2_0 (0x2 << 6) +#define GEN7_WM_DW1_AA_LINE_WIDTH_4_0 (0x3 << 6) +#define GEN7_WM_DW1_POLY_STIPPLE_ENABLE (0x1 << 4) +#define GEN7_WM_DW1_LINE_STIPPLE_ENABLE (0x1 << 3) +#define GEN7_WM_DW1_POINT_RASTRULE__MASK 0x00000004 +#define GEN7_WM_DW1_POINT_RASTRULE__SHIFT 2 +#define GEN7_WM_DW1_POINT_RASTRULE_UPPER_LEFT (0x0 << 2) +#define GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT (0x1 << 2) +#define GEN7_WM_DW1_MSRASTMODE__MASK 0x00000003 +#define GEN7_WM_DW1_MSRASTMODE__SHIFT 0 +#define GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL 0x0 +#define GEN7_WM_DW1_MSRASTMODE_OFF_PATTERN 0x1 +#define GEN7_WM_DW1_MSRASTMODE_ON_PIXEL 0x2 +#define GEN7_WM_DW1_MSRASTMODE_ON_PATTERN 0x3 + +#define GEN7_WM_DW2_MSDISPMODE__MASK 0x80000000 +#define GEN7_WM_DW2_MSDISPMODE__SHIFT 31 +#define GEN7_WM_DW2_MSDISPMODE_PERSAMPLE (0x0 << 31) +#define GEN7_WM_DW2_MSDISPMODE_PERPIXEL (0x1 << 31) + +#define GEN7_3DSTATE_PS__SIZE 8 + + +#define GEN7_PS_DW1_KERNEL0_ADDR__MASK 0xffffffc0 +#define GEN7_PS_DW1_KERNEL0_ADDR__SHIFT 6 +#define GEN7_PS_DW1_KERNEL0_ADDR__SHR 6 + + + +#define GEN7_PS_DW4_MAX_THREADS__MASK 0xff000000 +#define GEN7_PS_DW4_MAX_THREADS__SHIFT 24 +#define GEN75_PS_DW4_MAX_THREADS__MASK 0xff800000 +#define GEN75_PS_DW4_MAX_THREADS__SHIFT 23 +#define GEN75_PS_DW4_SAMPLE_MASK__MASK 0x000ff000 +#define GEN75_PS_DW4_SAMPLE_MASK__SHIFT 12 +#define GEN7_PS_DW4_PUSH_CONSTANT_ENABLE (0x1 << 11) +#define GEN7_PS_DW4_ATTR_ENABLE (0x1 << 10) +#define GEN7_PS_DW4_PS_COMPUTE_OMASK (0x1 << 9) +#define GEN7_PS_DW4_RT_FAST_CLEAR (0x1 << 8) +#define GEN7_PS_DW4_DUAL_SOURCE_BLEND (0x1 << 7) +#define GEN7_PS_DW4_RT_RESOLVE (0x1 << 6) +#define GEN75_PS_DW4_PS_ACCESS_UAV (0x1 << 5) +#define GEN7_PS_DW4_POSOFFSET__MASK 0x00000018 +#define GEN7_PS_DW4_POSOFFSET__SHIFT 3 +#define GEN7_PS_DW4_POSOFFSET_NONE (0x0 << 3) +#define GEN7_PS_DW4_POSOFFSET_CENTROID (0x2 << 3) +#define GEN7_PS_DW4_POSOFFSET_SAMPLE (0x3 << 3) +#define GEN7_PS_DW4_32_PIXEL_DISPATCH (0x1 << 2) +#define GEN7_PS_DW4_16_PIXEL_DISPATCH (0x1 << 1) +#define GEN7_PS_DW4_8_PIXEL_DISPATCH (0x1 << 0) + +#define GEN7_PS_DW5_URB_GRF_START0__MASK 0x007f0000 +#define GEN7_PS_DW5_URB_GRF_START0__SHIFT 16 +#define GEN7_PS_DW5_URB_GRF_START1__MASK 0x00007f00 +#define GEN7_PS_DW5_URB_GRF_START1__SHIFT 8 +#define GEN7_PS_DW5_URB_GRF_START2__MASK 0x0000007f +#define GEN7_PS_DW5_URB_GRF_START2__SHIFT 0 + +#define GEN7_PS_DW6_KERNEL1_ADDR__MASK 0xffffffc0 +#define GEN7_PS_DW6_KERNEL1_ADDR__SHIFT 6 +#define GEN7_PS_DW6_KERNEL1_ADDR__SHR 6 + +#define GEN7_PS_DW7_KERNEL2_ADDR__MASK 0xffffffc0 +#define GEN7_PS_DW7_KERNEL2_ADDR__SHIFT 6 +#define GEN7_PS_DW7_KERNEL2_ADDR__SHR 6 + +#define GEN6_3DSTATE_CONSTANT_ANY__SIZE 7 + +#define GEN6_PCB_ANY_DW0_PCB3_VALID (0x1 << 15) +#define GEN6_PCB_ANY_DW0_PCB2_VALID (0x1 << 14) +#define GEN6_PCB_ANY_DW0_PCB1_VALID (0x1 << 13) +#define GEN6_PCB_ANY_DW0_PCB0_VALID (0x1 << 12) +#define GEN6_PCB_ANY_DW0_MOCS__MASK 0x00000f00 +#define GEN6_PCB_ANY_DW0_MOCS__SHIFT 8 + +#define GEN6_PCB_ANY_SIZE__MASK 0x0000001f +#define GEN6_PCB_ANY_SIZE__SHIFT 0 +#define GEN6_PCB_ANY_ADDR__MASK 0xffffffe0 +#define GEN6_PCB_ANY_ADDR__SHIFT 5 +#define GEN6_PCB_ANY_ADDR__SHR 5 + + + +#define GEN7_PCB_ANY_DW1_PCB1_SIZE__MASK 0xffff0000 +#define GEN7_PCB_ANY_DW1_PCB1_SIZE__SHIFT 16 +#define GEN7_PCB_ANY_DW1_PCB0_SIZE__MASK 0x0000ffff +#define GEN7_PCB_ANY_DW1_PCB0_SIZE__SHIFT 0 + +#define GEN7_PCB_ANY_DW2_PCB3_SIZE__MASK 0xffff0000 +#define GEN7_PCB_ANY_DW2_PCB3_SIZE__SHIFT 16 +#define GEN7_PCB_ANY_DW2_PCB2_SIZE__MASK 0x0000ffff +#define GEN7_PCB_ANY_DW2_PCB2_SIZE__SHIFT 0 + +#define GEN7_PCB_ANY_MOCS__MASK 0x0000001f +#define GEN7_PCB_ANY_MOCS__SHIFT 0 +#define GEN7_PCB_ANY_ADDR__MASK 0xffffffe0 +#define GEN7_PCB_ANY_ADDR__SHIFT 5 +#define GEN7_PCB_ANY_ADDR__SHR 5 + +#define GEN6_3DSTATE_SAMPLE_MASK__SIZE 2 + + +#define GEN6_SAMPLE_MASK_DW1_VAL__MASK 0x0000000f +#define GEN6_SAMPLE_MASK_DW1_VAL__SHIFT 0 +#define GEN7_SAMPLE_MASK_DW1_VAL__MASK 0x000000ff +#define GEN7_SAMPLE_MASK_DW1_VAL__SHIFT 0 + +#define GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE 4 + + +#define GEN6_DRAWING_RECTANGLE_DW1_MIN_Y__MASK 0xffff0000 +#define GEN6_DRAWING_RECTANGLE_DW1_MIN_Y__SHIFT 16 +#define GEN6_DRAWING_RECTANGLE_DW1_MIN_X__MASK 0x0000ffff +#define GEN6_DRAWING_RECTANGLE_DW1_MIN_X__SHIFT 0 + +#define GEN6_DRAWING_RECTANGLE_DW2_MAX_Y__MASK 0xffff0000 +#define GEN6_DRAWING_RECTANGLE_DW2_MAX_Y__SHIFT 16 +#define GEN6_DRAWING_RECTANGLE_DW2_MAX_X__MASK 0x0000ffff +#define GEN6_DRAWING_RECTANGLE_DW2_MAX_X__SHIFT 0 + +#define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_Y__MASK 0xffff0000 +#define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_Y__SHIFT 16 +#define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_X__MASK 0x0000ffff +#define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_X__SHIFT 0 + +#define GEN6_3DSTATE_DEPTH_BUFFER__SIZE 7 + + +#define GEN6_DEPTH_DW1_TYPE__MASK 0xe0000000 +#define GEN6_DEPTH_DW1_TYPE__SHIFT 29 +#define GEN6_DEPTH_DW1_TILING__MASK 0x0c000000 +#define GEN6_DEPTH_DW1_TILING__SHIFT 26 +#define GEN6_DEPTH_DW1_STR_MODE__MASK 0x01800000 +#define GEN6_DEPTH_DW1_STR_MODE__SHIFT 23 +#define GEN6_DEPTH_DW1_HIZ_ENABLE (0x1 << 22) +#define GEN6_DEPTH_DW1_SEPARATE_STENCIL (0x1 << 21) +#define GEN6_DEPTH_DW1_FORMAT__MASK 0x001c0000 +#define GEN6_DEPTH_DW1_FORMAT__SHIFT 18 +#define GEN6_DEPTH_DW1_PITCH__MASK 0x0001ffff +#define GEN6_DEPTH_DW1_PITCH__SHIFT 0 + + +#define GEN6_DEPTH_DW3_HEIGHT__MASK 0xfff80000 +#define GEN6_DEPTH_DW3_HEIGHT__SHIFT 19 +#define GEN6_DEPTH_DW3_WIDTH__MASK 0x0007ffc0 +#define GEN6_DEPTH_DW3_WIDTH__SHIFT 6 +#define GEN6_DEPTH_DW3_LOD__MASK 0x0000003c +#define GEN6_DEPTH_DW3_LOD__SHIFT 2 +#define GEN6_DEPTH_DW3_MIPLAYOUT__MASK 0x00000002 +#define GEN6_DEPTH_DW3_MIPLAYOUT__SHIFT 1 +#define GEN6_DEPTH_DW3_MIPLAYOUT_BELOW (0x0 << 1) +#define GEN6_DEPTH_DW3_MIPLAYOUT_RIGHT (0x1 << 1) + +#define GEN6_DEPTH_DW4_DEPTH__MASK 0xffe00000 +#define GEN6_DEPTH_DW4_DEPTH__SHIFT 21 +#define GEN6_DEPTH_DW4_MIN_ARRAY_ELEMENT__MASK 0x001ffc00 +#define GEN6_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT 10 +#define GEN6_DEPTH_DW4_RT_VIEW_EXTENT__MASK 0x000003fe +#define GEN6_DEPTH_DW4_RT_VIEW_EXTENT__SHIFT 1 + +#define GEN6_DEPTH_DW5_OFFSET_Y__MASK 0xffff0000 +#define GEN6_DEPTH_DW5_OFFSET_Y__SHIFT 16 +#define GEN6_DEPTH_DW5_OFFSET_X__MASK 0x0000ffff +#define GEN6_DEPTH_DW5_OFFSET_X__SHIFT 0 + +#define GEN6_DEPTH_DW6_MOCS__MASK 0xf8000000 +#define GEN6_DEPTH_DW6_MOCS__SHIFT 27 + + + +#define GEN7_DEPTH_DW1_TYPE__MASK 0xe0000000 +#define GEN7_DEPTH_DW1_TYPE__SHIFT 29 +#define GEN7_DEPTH_DW1_DEPTH_WRITE_ENABLE (0x1 << 28) +#define GEN7_DEPTH_DW1_STENCIL_WRITE_ENABLE (0x1 << 27) +#define GEN7_DEPTH_DW1_HIZ_ENABLE (0x1 << 22) +#define GEN7_DEPTH_DW1_FORMAT__MASK 0x001c0000 +#define GEN7_DEPTH_DW1_FORMAT__SHIFT 18 +#define GEN7_DEPTH_DW1_PITCH__MASK 0x0003ffff +#define GEN7_DEPTH_DW1_PITCH__SHIFT 0 + + +#define GEN7_DEPTH_DW3_HEIGHT__MASK 0xfffc0000 +#define GEN7_DEPTH_DW3_HEIGHT__SHIFT 18 +#define GEN7_DEPTH_DW3_WIDTH__MASK 0x0003fff0 +#define GEN7_DEPTH_DW3_WIDTH__SHIFT 4 +#define GEN7_DEPTH_DW3_LOD__MASK 0x0000000f +#define GEN7_DEPTH_DW3_LOD__SHIFT 0 + +#define GEN7_DEPTH_DW4_DEPTH__MASK 0xffe00000 +#define GEN7_DEPTH_DW4_DEPTH__SHIFT 21 +#define GEN7_DEPTH_DW4_MIN_ARRAY_ELEMENT__MASK 0x001ffc00 +#define GEN7_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT 10 +#define GEN7_DEPTH_DW4_MOCS__MASK 0x0000000f +#define GEN7_DEPTH_DW4_MOCS__SHIFT 0 + +#define GEN7_DEPTH_DW5_OFFSET_Y__MASK 0xffff0000 +#define GEN7_DEPTH_DW5_OFFSET_Y__SHIFT 16 +#define GEN7_DEPTH_DW5_OFFSET_X__MASK 0x0000ffff +#define GEN7_DEPTH_DW5_OFFSET_X__SHIFT 0 + +#define GEN7_DEPTH_DW6_RT_VIEW_EXTENT__MASK 0xffe00000 +#define GEN7_DEPTH_DW6_RT_VIEW_EXTENT__SHIFT 21 + +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE 2 + + +#define GEN6_POLY_STIPPLE_OFFSET_DW1_X__MASK 0x00001f00 +#define GEN6_POLY_STIPPLE_OFFSET_DW1_X__SHIFT 8 +#define GEN6_POLY_STIPPLE_OFFSET_DW1_Y__MASK 0x0000001f +#define GEN6_POLY_STIPPLE_OFFSET_DW1_Y__SHIFT 0 + +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE 33 + + + +#define GEN6_3DSTATE_LINE_STIPPLE__SIZE 3 + + +#define GEN6_LINE_STIPPLE_DW1_PATTERN__MASK 0x0000ffff +#define GEN6_LINE_STIPPLE_DW1_PATTERN__SHIFT 0 + +#define GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__MASK 0xffff0000 +#define GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT 16 +#define GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__RADIX 13 +#define GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__MASK 0xffff8000 +#define GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT 15 +#define GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__RADIX 16 +#define GEN6_LINE_STIPPLE_DW2_REPEAT_COUNT__MASK 0x000001ff +#define GEN6_LINE_STIPPLE_DW2_REPEAT_COUNT__SHIFT 0 + +#define GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE 3 + + +#define GEN6_AA_LINE_DW1_BIAS__MASK 0x00ff0000 +#define GEN6_AA_LINE_DW1_BIAS__SHIFT 16 +#define GEN6_AA_LINE_DW1_BIAS__RADIX 8 +#define GEN6_AA_LINE_DW1_SLOPE__MASK 0x000000ff +#define GEN6_AA_LINE_DW1_SLOPE__SHIFT 0 +#define GEN6_AA_LINE_DW1_SLOPE__RADIX 8 + +#define GEN6_AA_LINE_DW2_CAP_BIAS__MASK 0x00ff0000 +#define GEN6_AA_LINE_DW2_CAP_BIAS__SHIFT 16 +#define GEN6_AA_LINE_DW2_CAP_BIAS__RADIX 8 +#define GEN6_AA_LINE_DW2_CAP_SLOPE__MASK 0x000000ff +#define GEN6_AA_LINE_DW2_CAP_SLOPE__SHIFT 0 +#define GEN6_AA_LINE_DW2_CAP_SLOPE__RADIX 8 + +#define GEN6_3DSTATE_GS_SVB_INDEX__SIZE 4 + + +#define GEN6_SVBI_DW1_INDEX__MASK 0x60000000 +#define GEN6_SVBI_DW1_INDEX__SHIFT 29 +#define GEN6_SVBI_DW1_LOAD_INTERNAL_VERTEX_COUNT (0x1 << 0) + + + +#define GEN6_3DSTATE_MULTISAMPLE__SIZE 4 + + +#define GEN75_MULTISAMPLE_DW1_DX9_MULTISAMPLE_ENABLE (0x1 << 5) +#define GEN6_MULTISAMPLE_DW1_PIXLOC__MASK 0x00000010 +#define GEN6_MULTISAMPLE_DW1_PIXLOC__SHIFT 4 +#define GEN6_MULTISAMPLE_DW1_PIXLOC_CENTER (0x0 << 4) +#define GEN6_MULTISAMPLE_DW1_PIXLOC_UL_CORNER (0x1 << 4) +#define GEN6_MULTISAMPLE_DW1_NUMSAMPLES__MASK 0x0000000e +#define GEN6_MULTISAMPLE_DW1_NUMSAMPLES__SHIFT 1 +#define GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1 (0x0 << 1) +#define GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4 (0x2 << 1) +#define GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8 (0x3 << 1) + + + +#define GEN6_3DSTATE_STENCIL_BUFFER__SIZE 3 + + +#define GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE (0x1 << 31) +#define GEN6_STENCIL_DW1_MOCS__MASK 0x1e000000 +#define GEN6_STENCIL_DW1_MOCS__SHIFT 25 +#define GEN6_STENCIL_DW1_PITCH__MASK 0x0001ffff +#define GEN6_STENCIL_DW1_PITCH__SHIFT 0 + + +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE 3 + + +#define GEN6_HIZ_DW1_MOCS__MASK 0x1e000000 +#define GEN6_HIZ_DW1_MOCS__SHIFT 25 +#define GEN6_HIZ_DW1_PITCH__MASK 0x0001ffff +#define GEN6_HIZ_DW1_PITCH__SHIFT 0 + + +#define GEN6_3DSTATE_CLEAR_PARAMS__SIZE 3 + +#define GEN6_CLEAR_PARAMS_DW0_VALID (0x1 << 15) + + + + + +#define GEN7_CLEAR_PARAMS_DW2_VALID (0x1 << 0) + +#define GEN6_PIPE_CONTROL__SIZE 5 + + +#define GEN7_PIPE_CONTROL_USE_GGTT (0x1 << 24) +#define GEN7_PIPE_CONTROL_LRI_WRITE__MASK 0x00800000 +#define GEN7_PIPE_CONTROL_LRI_WRITE__SHIFT 23 +#define GEN7_PIPE_CONTROL_LRI_WRITE_NONE (0x0 << 23) +#define GEN7_PIPE_CONTROL_LRI_WRITE_IMM (0x1 << 23) +#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_ENABLE (0x1 << 22) +#define GEN6_PIPE_CONTROL_STORE_DATA_INDEX (0x1 << 21) +#define GEN6_PIPE_CONTROL_CS_STALL (0x1 << 20) +#define GEN6_PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (0x1 << 19) +#define GEN6_PIPE_CONTROL_TLB_INVALIDATE (0x1 << 18) +#define GEN6_PIPE_CONTROL_SYNC_GFDT_SURFACE (0x1 << 17) +#define GEN6_PIPE_CONTROL_GENERIC_MEDIA_STATE_CLEAR (0x1 << 16) +#define GEN6_PIPE_CONTROL_WRITE__MASK 0x0000c000 +#define GEN6_PIPE_CONTROL_WRITE__SHIFT 14 +#define GEN6_PIPE_CONTROL_WRITE_NONE (0x0 << 14) +#define GEN6_PIPE_CONTROL_WRITE_IMM (0x1 << 14) +#define GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT (0x2 << 14) +#define GEN6_PIPE_CONTROL_WRITE_TIMESTAMP (0x3 << 14) +#define GEN6_PIPE_CONTROL_DEPTH_STALL (0x1 << 13) +#define GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH (0x1 << 12) +#define GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (0x1 << 11) +#define GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (0x1 << 10) +#define GEN6_PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE (0x1 << 9) +#define GEN6_PIPE_CONTROL_NOTIFY_ENABLE (0x1 << 8) +#define GEN7_PIPE_CONTROL_FLUSH_ENABLE (0x1 << 7) +#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__MASK 0x00000040 +#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__SHIFT 6 +#define GEN7_PIPE_CONTROL_DC_FLUSH_ENABLE (0x1 << 5) +#define GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE (0x1 << 4) +#define GEN6_PIPE_CONTROL_CONSTANT_CACHE_INVALIDATE (0x1 << 3) +#define GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE (0x1 << 2) +#define GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL (0x1 << 1) +#define GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH (0x1 << 0) + +#define GEN6_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffff8 +#define GEN6_PIPE_CONTROL_DW2_ADDR__SHIFT 3 +#define GEN6_PIPE_CONTROL_DW2_ADDR__SHR 3 +#define GEN6_PIPE_CONTROL_DW2_USE_GGTT (0x1 << 2) +#define GEN7_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffffc +#define GEN7_PIPE_CONTROL_DW2_ADDR__SHIFT 2 +#define GEN7_PIPE_CONTROL_DW2_ADDR__SHR 2 + + +#define GEN6_3DPRIMITIVE__SIZE 7 + +#define GEN6_3DPRIM_DW0_ACCESS__MASK 0x00008000 +#define GEN6_3DPRIM_DW0_ACCESS__SHIFT 15 +#define GEN6_3DPRIM_DW0_ACCESS_SEQUENTIAL (0x0 << 15) +#define GEN6_3DPRIM_DW0_ACCESS_RANDOM (0x1 << 15) +#define GEN6_3DPRIM_DW0_TYPE__MASK 0x00007c00 +#define GEN6_3DPRIM_DW0_TYPE__SHIFT 10 +#define GEN6_3DPRIM_DW0_USE_INTERNAL_VERTEX_COUNT (0x1 << 9) + + + + + + + +#define GEN7_3DPRIM_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10) +#define GEN7_3DPRIM_DW0_PREDICATE_ENABLE (0x1 << 8) + +#define GEN7_3DPRIM_DW1_END_OFFSET_ENABLE (0x1 << 9) +#define GEN7_3DPRIM_DW1_ACCESS__MASK 0x00000100 +#define GEN7_3DPRIM_DW1_ACCESS__SHIFT 8 +#define GEN7_3DPRIM_DW1_ACCESS_SEQUENTIAL (0x0 << 8) +#define GEN7_3DPRIM_DW1_ACCESS_RANDOM (0x1 << 8) +#define GEN7_3DPRIM_DW1_TYPE__MASK 0x0000003f +#define GEN7_3DPRIM_DW1_TYPE__SHIFT 0 + + + + + + + +#endif /* GEN_RENDER_3D_XML */ diff --git a/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h new file mode 100644 index 00000000000..f1bae49e26b --- /dev/null +++ b/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h @@ -0,0 +1,371 @@ +#ifndef GEN_RENDER_DYNAMIC_XML +#define GEN_RENDER_DYNAMIC_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +https://github.com/olvaffe/envytools/ +git clone https://github.com/olvaffe/envytools.git + +Copyright (C) 2014 by the following authors: +- Chia-I Wu <[email protected]> (olv) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define GEN6_COMPAREFUNCTION_ALWAYS 0x0 +#define GEN6_COMPAREFUNCTION_NEVER 0x1 +#define GEN6_COMPAREFUNCTION_LESS 0x2 +#define GEN6_COMPAREFUNCTION_EQUAL 0x3 +#define GEN6_COMPAREFUNCTION_LEQUAL 0x4 +#define GEN6_COMPAREFUNCTION_GREATER 0x5 +#define GEN6_COMPAREFUNCTION_NOTEQUAL 0x6 +#define GEN6_COMPAREFUNCTION_GEQUAL 0x7 +#define GEN6_STENCILOP_KEEP 0x0 +#define GEN6_STENCILOP_ZERO 0x1 +#define GEN6_STENCILOP_REPLACE 0x2 +#define GEN6_STENCILOP_INCRSAT 0x3 +#define GEN6_STENCILOP_DECRSAT 0x4 +#define GEN6_STENCILOP_INCR 0x5 +#define GEN6_STENCILOP_DECR 0x6 +#define GEN6_STENCILOP_INVERT 0x7 +#define GEN6_BLENDFACTOR_ONE 0x1 +#define GEN6_BLENDFACTOR_SRC_COLOR 0x2 +#define GEN6_BLENDFACTOR_SRC_ALPHA 0x3 +#define GEN6_BLENDFACTOR_DST_ALPHA 0x4 +#define GEN6_BLENDFACTOR_DST_COLOR 0x5 +#define GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 +#define GEN6_BLENDFACTOR_CONST_COLOR 0x7 +#define GEN6_BLENDFACTOR_CONST_ALPHA 0x8 +#define GEN6_BLENDFACTOR_SRC1_COLOR 0x9 +#define GEN6_BLENDFACTOR_SRC1_ALPHA 0xa +#define GEN6_BLENDFACTOR_ZERO 0x11 +#define GEN6_BLENDFACTOR_INV_SRC_COLOR 0x12 +#define GEN6_BLENDFACTOR_INV_SRC_ALPHA 0x13 +#define GEN6_BLENDFACTOR_INV_DST_ALPHA 0x14 +#define GEN6_BLENDFACTOR_INV_DST_COLOR 0x15 +#define GEN6_BLENDFACTOR_INV_CONST_COLOR 0x17 +#define GEN6_BLENDFACTOR_INV_CONST_ALPHA 0x18 +#define GEN6_BLENDFACTOR_INV_SRC1_COLOR 0x19 +#define GEN6_BLENDFACTOR_INV_SRC1_ALPHA 0x1a +#define GEN6_BLENDFUNCTION_ADD 0x0 +#define GEN6_BLENDFUNCTION_SUBTRACT 0x1 +#define GEN6_BLENDFUNCTION_REVERSE_SUBTRACT 0x2 +#define GEN6_BLENDFUNCTION_MIN 0x3 +#define GEN6_BLENDFUNCTION_MAX 0x4 +#define GEN6_LOGICOP_CLEAR 0x0 +#define GEN6_LOGICOP_NOR 0x1 +#define GEN6_LOGICOP_AND_INVERTED 0x2 +#define GEN6_LOGICOP_COPY_INVERTED 0x3 +#define GEN6_LOGICOP_AND_REVERSE 0x4 +#define GEN6_LOGICOP_INVERT 0x5 +#define GEN6_LOGICOP_XOR 0x6 +#define GEN6_LOGICOP_NAND 0x7 +#define GEN6_LOGICOP_AND 0x8 +#define GEN6_LOGICOP_EQUIV 0x9 +#define GEN6_LOGICOP_NOOP 0xa +#define GEN6_LOGICOP_OR_INVERTED 0xb +#define GEN6_LOGICOP_COPY 0xc +#define GEN6_LOGICOP_OR_REVERSE 0xd +#define GEN6_LOGICOP_OR 0xe +#define GEN6_LOGICOP_SET 0xf +#define GEN6_MIPFILTER_NONE 0x0 +#define GEN6_MIPFILTER_NEAREST 0x1 +#define GEN6_MIPFILTER_LINEAR 0x3 +#define GEN6_MAPFILTER_NEAREST 0x0 +#define GEN6_MAPFILTER_LINEAR 0x1 +#define GEN6_MAPFILTER_ANISOTROPIC 0x2 +#define GEN6_MAPFILTER_MONO 0x6 +#define GEN6_ANISORATIO_2 0x0 +#define GEN6_ANISORATIO_4 0x1 +#define GEN6_ANISORATIO_6 0x2 +#define GEN6_ANISORATIO_8 0x3 +#define GEN6_ANISORATIO_10 0x4 +#define GEN6_ANISORATIO_12 0x5 +#define GEN6_ANISORATIO_14 0x6 +#define GEN6_ANISORATIO_16 0x7 +#define GEN6_TEXCOORDMODE_WRAP 0x0 +#define GEN6_TEXCOORDMODE_MIRROR 0x1 +#define GEN6_TEXCOORDMODE_CLAMP 0x2 +#define GEN6_TEXCOORDMODE_CUBE 0x3 +#define GEN6_TEXCOORDMODE_CLAMP_BORDER 0x4 +#define GEN6_TEXCOORDMODE_MIRROR_ONCE 0x5 +#define GEN6_KEYFILTER_KILL_ON_ANY_MATCH 0x0 +#define GEN6_KEYFILTER_REPLACE_BLACK 0x1 +#define GEN6_COLOR_CALC_STATE__SIZE 6 + +#define GEN6_CC_DW0_STENCIL0_REF__MASK 0xff000000 +#define GEN6_CC_DW0_STENCIL0_REF__SHIFT 24 +#define GEN6_CC_DW0_STENCIL1_REF__MASK 0x00ff0000 +#define GEN6_CC_DW0_STENCIL1_REF__SHIFT 16 +#define GEN6_CC_DW0_ROUND_DISABLE_DISABLE (0x1 << 15) +#define GEN6_CC_DW0_ALPHATEST__MASK 0x00000001 +#define GEN6_CC_DW0_ALPHATEST__SHIFT 0 +#define GEN6_CC_DW0_ALPHATEST_UNORM8 0x0 +#define GEN6_CC_DW0_ALPHATEST_FLOAT32 0x1 + + + + + + +#define GEN6_DEPTH_STENCIL_STATE__SIZE 3 + +#define GEN6_ZS_DW0_STENCIL_TEST_ENABLE (0x1 << 31) +#define GEN6_ZS_DW0_STENCIL0_FUNC__MASK 0x70000000 +#define GEN6_ZS_DW0_STENCIL0_FUNC__SHIFT 28 +#define GEN6_ZS_DW0_STENCIL0_FAIL_OP__MASK 0x0e000000 +#define GEN6_ZS_DW0_STENCIL0_FAIL_OP__SHIFT 25 +#define GEN6_ZS_DW0_STENCIL0_ZFAIL_OP__MASK 0x01c00000 +#define GEN6_ZS_DW0_STENCIL0_ZFAIL_OP__SHIFT 22 +#define GEN6_ZS_DW0_STENCIL0_ZPASS_OP__MASK 0x00380000 +#define GEN6_ZS_DW0_STENCIL0_ZPASS_OP__SHIFT 19 +#define GEN6_ZS_DW0_STENCIL_WRITE_ENABLE (0x1 << 18) +#define GEN6_ZS_DW0_STENCIL1_ENABLE (0x1 << 15) +#define GEN6_ZS_DW0_STENCIL1_FUNC__MASK 0x00007000 +#define GEN6_ZS_DW0_STENCIL1_FUNC__SHIFT 12 +#define GEN6_ZS_DW0_STENCIL1_FAIL_OP__MASK 0x00000e00 +#define GEN6_ZS_DW0_STENCIL1_FAIL_OP__SHIFT 9 +#define GEN6_ZS_DW0_STENCIL1_ZFAIL_OP__MASK 0x000001c0 +#define GEN6_ZS_DW0_STENCIL1_ZFAIL_OP__SHIFT 6 +#define GEN6_ZS_DW0_STENCIL1_ZPASS_OP__MASK 0x00000038 +#define GEN6_ZS_DW0_STENCIL1_ZPASS_OP__SHIFT 3 + +#define GEN6_ZS_DW1_STENCIL0_VALUEMASK__MASK 0xff000000 +#define GEN6_ZS_DW1_STENCIL0_VALUEMASK__SHIFT 24 +#define GEN6_ZS_DW1_STENCIL0_WRITEMASK__MASK 0x00ff0000 +#define GEN6_ZS_DW1_STENCIL0_WRITEMASK__SHIFT 16 +#define GEN6_ZS_DW1_STENCIL1_VALUEMASK__MASK 0x0000ff00 +#define GEN6_ZS_DW1_STENCIL1_VALUEMASK__SHIFT 8 +#define GEN6_ZS_DW1_STENCIL1_WRITEMASK__MASK 0x000000ff +#define GEN6_ZS_DW1_STENCIL1_WRITEMASK__SHIFT 0 + +#define GEN6_ZS_DW2_DEPTH_TEST_ENABLE (0x1 << 31) +#define GEN6_ZS_DW2_DEPTH_FUNC__MASK 0x38000000 +#define GEN6_ZS_DW2_DEPTH_FUNC__SHIFT 27 +#define GEN6_ZS_DW2_DEPTH_WRITE_ENABLE (0x1 << 26) + +#define GEN6_BLEND_STATE__SIZE 2 + +#define GEN6_BLEND_DW0_BLEND_ENABLE (0x1 << 31) +#define GEN6_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE (0x1 << 30) +#define GEN6_BLEND_DW0_ALPHA_FUNC__MASK 0x1c000000 +#define GEN6_BLEND_DW0_ALPHA_FUNC__SHIFT 26 +#define GEN6_BLEND_DW0_SRC_ALPHA_FACTOR__MASK 0x01f00000 +#define GEN6_BLEND_DW0_SRC_ALPHA_FACTOR__SHIFT 20 +#define GEN6_BLEND_DW0_DST_ALPHA_FACTOR__MASK 0x000f8000 +#define GEN6_BLEND_DW0_DST_ALPHA_FACTOR__SHIFT 15 +#define GEN6_BLEND_DW0_COLOR_FUNC__MASK 0x00003800 +#define GEN6_BLEND_DW0_COLOR_FUNC__SHIFT 11 +#define GEN6_BLEND_DW0_SRC_COLOR_FACTOR__MASK 0x000003e0 +#define GEN6_BLEND_DW0_SRC_COLOR_FACTOR__SHIFT 5 +#define GEN6_BLEND_DW0_DST_COLOR_FACTOR__MASK 0x0000001f +#define GEN6_BLEND_DW0_DST_COLOR_FACTOR__SHIFT 0 + +#define GEN6_BLEND_DW1_ALPHA_TO_COVERAGE (0x1 << 31) +#define GEN6_BLEND_DW1_ALPHA_TO_ONE (0x1 << 30) +#define GEN6_BLEND_DW1_ALPHA_TO_COVERAGE_DITHER (0x1 << 29) +#define GEN6_BLEND_DW1_WRITE_DISABLE_A (0x1 << 27) +#define GEN6_BLEND_DW1_WRITE_DISABLE_R (0x1 << 26) +#define GEN6_BLEND_DW1_WRITE_DISABLE_G (0x1 << 25) +#define GEN6_BLEND_DW1_WRITE_DISABLE_B (0x1 << 24) +#define GEN6_BLEND_DW1_LOGICOP_ENABLE (0x1 << 22) +#define GEN6_BLEND_DW1_LOGICOP_FUNC__MASK 0x003c0000 +#define GEN6_BLEND_DW1_LOGICOP_FUNC__SHIFT 18 +#define GEN6_BLEND_DW1_ALPHA_TEST_ENABLE (0x1 << 16) +#define GEN6_BLEND_DW1_ALPHA_TEST_FUNC__MASK 0x0000e000 +#define GEN6_BLEND_DW1_ALPHA_TEST_FUNC__SHIFT 13 +#define GEN6_BLEND_DW1_DITHER_ENABLE (0x1 << 12) +#define GEN6_BLEND_DW1_X_DITHER_OFFSET__MASK 0x00000c00 +#define GEN6_BLEND_DW1_X_DITHER_OFFSET__SHIFT 10 +#define GEN6_BLEND_DW1_Y_DITHER_OFFSET__MASK 0x00000300 +#define GEN6_BLEND_DW1_Y_DITHER_OFFSET__SHIFT 8 +#define GEN6_BLEND_DW1_COLORCLAMP__MASK 0x0000000c +#define GEN6_BLEND_DW1_COLORCLAMP__SHIFT 2 +#define GEN6_BLEND_DW1_COLORCLAMP_UNORM (0x0 << 2) +#define GEN6_BLEND_DW1_COLORCLAMP_SNORM (0x1 << 2) +#define GEN6_BLEND_DW1_COLORCLAMP_RTFORMAT (0x2 << 2) +#define GEN6_BLEND_DW1_PRE_BLEND_CLAMP (0x1 << 1) +#define GEN6_BLEND_DW1_POST_BLEND_CLAMP (0x1 << 0) + +#define GEN6_CLIP_VIEWPORT__SIZE 4 + + + + + +#define GEN6_SF_VIEWPORT__SIZE 8 + + + + + + + +#define GEN7_SF_CLIP_VIEWPORT__SIZE 16 + + + +#define GEN6_CC_VIEWPORT__SIZE 2 + + + +#define GEN6_SCISSOR_RECT__SIZE 2 + +#define GEN6_SCISSOR_DW0_MIN_Y__MASK 0xffff0000 +#define GEN6_SCISSOR_DW0_MIN_Y__SHIFT 16 +#define GEN6_SCISSOR_DW0_MIN_X__MASK 0x0000ffff +#define GEN6_SCISSOR_DW0_MIN_X__SHIFT 0 + +#define GEN6_SCISSOR_DW1_MAX_Y__MASK 0xffff0000 +#define GEN6_SCISSOR_DW1_MAX_Y__SHIFT 16 +#define GEN6_SCISSOR_DW1_MAX_X__MASK 0x0000ffff +#define GEN6_SCISSOR_DW1_MAX_X__SHIFT 0 + +#define GEN6_SAMPLER_BORDER_COLOR__SIZE 12 + + + +#define GEN6_SAMPLER_STATE__SIZE 4 + +#define GEN6_SAMPLER_DW0_DISABLE (0x1 << 31) +#define GEN6_SAMPLER_DW0_LOD_PRECLAMP_ENABLE (0x1 << 28) +#define GEN6_SAMPLER_DW0_MIN_MAG_NOT_EQUAL (0x1 << 27) +#define GEN6_SAMPLER_DW0_BASE_LOD__MASK 0x07c00000 +#define GEN6_SAMPLER_DW0_BASE_LOD__SHIFT 22 +#define GEN6_SAMPLER_DW0_MIP_FILTER__MASK 0x00300000 +#define GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT 20 +#define GEN6_SAMPLER_DW0_MAG_FILTER__MASK 0x000e0000 +#define GEN6_SAMPLER_DW0_MAG_FILTER__SHIFT 17 +#define GEN6_SAMPLER_DW0_MIN_FILTER__MASK 0x0001c000 +#define GEN6_SAMPLER_DW0_MIN_FILTER__SHIFT 14 +#define GEN6_SAMPLER_DW0_LOD_BIAS__MASK 0x00003ff8 +#define GEN6_SAMPLER_DW0_LOD_BIAS__SHIFT 3 +#define GEN6_SAMPLER_DW0_LOD_BIAS__RADIX 6 +#define GEN6_SAMPLER_DW0_SHADOW_FUNC__MASK 0x00000007 +#define GEN6_SAMPLER_DW0_SHADOW_FUNC__SHIFT 0 + +#define GEN6_SAMPLER_DW1_MIN_LOD__MASK 0xffc00000 +#define GEN6_SAMPLER_DW1_MIN_LOD__SHIFT 22 +#define GEN6_SAMPLER_DW1_MIN_LOD__RADIX 6 +#define GEN6_SAMPLER_DW1_MAX_LOD__MASK 0x003ff000 +#define GEN6_SAMPLER_DW1_MAX_LOD__SHIFT 12 +#define GEN6_SAMPLER_DW1_MAX_LOD__RADIX 6 +#define GEN6_SAMPLER_DW1_CUBECTRLMODE__MASK 0x00000200 +#define GEN6_SAMPLER_DW1_CUBECTRLMODE__SHIFT 9 +#define GEN6_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED (0x0 << 9) +#define GEN6_SAMPLER_DW1_CUBECTRLMODE_OVERRIDE (0x1 << 9) +#define GEN6_SAMPLER_DW1_U_WRAP__MASK 0x000001c0 +#define GEN6_SAMPLER_DW1_U_WRAP__SHIFT 6 +#define GEN6_SAMPLER_DW1_V_WRAP__MASK 0x00000038 +#define GEN6_SAMPLER_DW1_V_WRAP__SHIFT 3 +#define GEN6_SAMPLER_DW1_R_WRAP__MASK 0x00000007 +#define GEN6_SAMPLER_DW1_R_WRAP__SHIFT 0 + +#define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__MASK 0xffffffe0 +#define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHIFT 5 +#define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHR 5 + +#define GEN6_SAMPLER_DW3_CHROMAKEY_ENABLE (0x1 << 25) +#define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__MASK 0x01800000 +#define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__SHIFT 23 +#define GEN6_SAMPLER_DW3_CHROMAKEY_MODE__MASK 0x00400000 +#define GEN6_SAMPLER_DW3_CHROMAKEY_MODE__SHIFT 22 +#define GEN6_SAMPLER_DW3_MAX_ANISO__MASK 0x00380000 +#define GEN6_SAMPLER_DW3_MAX_ANISO__SHIFT 19 +#define GEN6_SAMPLER_DW3_U_MAG_ROUND (0x1 << 18) +#define GEN6_SAMPLER_DW3_U_MIN_ROUND (0x1 << 17) +#define GEN6_SAMPLER_DW3_V_MAG_ROUND (0x1 << 16) +#define GEN6_SAMPLER_DW3_V_MIN_ROUND (0x1 << 15) +#define GEN6_SAMPLER_DW3_R_MAG_ROUND (0x1 << 14) +#define GEN6_SAMPLER_DW3_R_MIN_ROUND (0x1 << 13) +#define GEN6_SAMPLER_DW3_NON_NORMALIZED_COORD (0x1 << 0) + + +#define GEN7_SAMPLER_DW0_DISABLE (0x1 << 31) +#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__MASK 0x20000000 +#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__SHIFT 29 +#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX10_OGL (0x0 << 29) +#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX9 (0x1 << 29) +#define GEN7_SAMPLER_DW0_LOD_PRECLAMP_ENABLE (0x1 << 28) +#define GEN7_SAMPLER_DW0_BASE_LOD__MASK 0x07c00000 +#define GEN7_SAMPLER_DW0_BASE_LOD__SHIFT 22 +#define GEN7_SAMPLER_DW0_MIP_FILTER__MASK 0x00300000 +#define GEN7_SAMPLER_DW0_MIP_FILTER__SHIFT 20 +#define GEN7_SAMPLER_DW0_MAG_FILTER__MASK 0x000e0000 +#define GEN7_SAMPLER_DW0_MAG_FILTER__SHIFT 17 +#define GEN7_SAMPLER_DW0_MIN_FILTER__MASK 0x0001c000 +#define GEN7_SAMPLER_DW0_MIN_FILTER__SHIFT 14 +#define GEN7_SAMPLER_DW0_LOD_BIAS__MASK 0x00003ffe +#define GEN7_SAMPLER_DW0_LOD_BIAS__SHIFT 1 +#define GEN7_SAMPLER_DW0_LOD_BIAS__RADIX 8 +#define GEN7_SAMPLER_DW0_ANISO_ALGO__MASK 0x00000001 +#define GEN7_SAMPLER_DW0_ANISO_ALGO__SHIFT 0 +#define GEN7_SAMPLER_DW0_ANISO_ALGO_LEGACY 0x0 +#define GEN7_SAMPLER_DW0_ANISO_ALGO_EWA 0x1 + +#define GEN7_SAMPLER_DW1_MIN_LOD__MASK 0xfff00000 +#define GEN7_SAMPLER_DW1_MIN_LOD__SHIFT 20 +#define GEN7_SAMPLER_DW1_MIN_LOD__RADIX 8 +#define GEN7_SAMPLER_DW1_MAX_LOD__MASK 0x000fff00 +#define GEN7_SAMPLER_DW1_MAX_LOD__SHIFT 8 +#define GEN7_SAMPLER_DW1_MAX_LOD__RADIX 8 +#define GEN7_SAMPLER_DW1_SHADOW_FUNC__MASK 0x0000000e +#define GEN7_SAMPLER_DW1_SHADOW_FUNC__SHIFT 1 +#define GEN7_SAMPLER_DW1_CUBECTRLMODE__MASK 0x00000001 +#define GEN7_SAMPLER_DW1_CUBECTRLMODE__SHIFT 0 +#define GEN7_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED 0x0 +#define GEN7_SAMPLER_DW1_CUBECTRLMODE_OVERRIDE 0x1 + +#define GEN7_SAMPLER_DW2_BORDER_COLOR_ADDR__MASK 0xffffffe0 +#define GEN7_SAMPLER_DW2_BORDER_COLOR_ADDR__SHIFT 5 +#define GEN7_SAMPLER_DW2_BORDER_COLOR_ADDR__SHR 5 + +#define GEN7_SAMPLER_DW3_CHROMAKEY_ENABLE (0x1 << 25) +#define GEN7_SAMPLER_DW3_CHROMAKEY_INDEX__MASK 0x01800000 +#define GEN7_SAMPLER_DW3_CHROMAKEY_INDEX__SHIFT 23 +#define GEN7_SAMPLER_DW3_CHROMAKEY_MODE__MASK 0x00400000 +#define GEN7_SAMPLER_DW3_CHROMAKEY_MODE__SHIFT 22 +#define GEN7_SAMPLER_DW3_MAX_ANISO__MASK 0x00380000 +#define GEN7_SAMPLER_DW3_MAX_ANISO__SHIFT 19 +#define GEN7_SAMPLER_DW3_U_MAG_ROUND (0x1 << 18) +#define GEN7_SAMPLER_DW3_U_MIN_ROUND (0x1 << 17) +#define GEN7_SAMPLER_DW3_V_MAG_ROUND (0x1 << 16) +#define GEN7_SAMPLER_DW3_V_MIN_ROUND (0x1 << 15) +#define GEN7_SAMPLER_DW3_R_MAG_ROUND (0x1 << 14) +#define GEN7_SAMPLER_DW3_R_MIN_ROUND (0x1 << 13) +#define GEN7_SAMPLER_DW3_TRIQUAL__MASK 0x00001800 +#define GEN7_SAMPLER_DW3_TRIQUAL__SHIFT 11 +#define GEN7_SAMPLER_DW3_TRIQUAL_FULL (0x0 << 11) +#define GEN75_SAMPLER_DW3_TRIQUAL_HIGH (0x1 << 11) +#define GEN7_SAMPLER_DW3_TRIQUAL_MED (0x2 << 11) +#define GEN7_SAMPLER_DW3_TRIQUAL_LOW (0x3 << 11) +#define GEN7_SAMPLER_DW3_NON_NORMALIZED_COORD (0x1 << 10) +#define GEN7_SAMPLER_DW3_U_WRAP__MASK 0x000001c0 +#define GEN7_SAMPLER_DW3_U_WRAP__SHIFT 6 +#define GEN7_SAMPLER_DW3_V_WRAP__MASK 0x00000038 +#define GEN7_SAMPLER_DW3_V_WRAP__SHIFT 3 +#define GEN7_SAMPLER_DW3_R_WRAP__MASK 0x00000007 +#define GEN7_SAMPLER_DW3_R_WRAP__SHIFT 0 + + +#endif /* GEN_RENDER_DYNAMIC_XML */ diff --git a/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h new file mode 100644 index 00000000000..f1ffd4ff42e --- /dev/null +++ b/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h @@ -0,0 +1,470 @@ +#ifndef GEN_RENDER_SURFACE_XML +#define GEN_RENDER_SURFACE_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +https://github.com/olvaffe/envytools/ +git clone https://github.com/olvaffe/envytools.git + +Copyright (C) 2014 by the following authors: +- Chia-I Wu <[email protected]> (olv) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define GEN6_FORMAT_R32G32B32A32_FLOAT 0x0 +#define GEN6_FORMAT_R32G32B32A32_SINT 0x1 +#define GEN6_FORMAT_R32G32B32A32_UINT 0x2 +#define GEN6_FORMAT_R32G32B32A32_UNORM 0x3 +#define GEN6_FORMAT_R32G32B32A32_SNORM 0x4 +#define GEN6_FORMAT_R64G64_FLOAT 0x5 +#define GEN6_FORMAT_R32G32B32X32_FLOAT 0x6 +#define GEN6_FORMAT_R32G32B32A32_SSCALED 0x7 +#define GEN6_FORMAT_R32G32B32A32_USCALED 0x8 +#define GEN6_FORMAT_R32G32B32A32_SFIXED 0x20 +#define GEN6_FORMAT_R64G64_PASSTHRU 0x21 +#define GEN6_FORMAT_R32G32B32_FLOAT 0x40 +#define GEN6_FORMAT_R32G32B32_SINT 0x41 +#define GEN6_FORMAT_R32G32B32_UINT 0x42 +#define GEN6_FORMAT_R32G32B32_UNORM 0x43 +#define GEN6_FORMAT_R32G32B32_SNORM 0x44 +#define GEN6_FORMAT_R32G32B32_SSCALED 0x45 +#define GEN6_FORMAT_R32G32B32_USCALED 0x46 +#define GEN6_FORMAT_R32G32B32_SFIXED 0x50 +#define GEN6_FORMAT_R16G16B16A16_UNORM 0x80 +#define GEN6_FORMAT_R16G16B16A16_SNORM 0x81 +#define GEN6_FORMAT_R16G16B16A16_SINT 0x82 +#define GEN6_FORMAT_R16G16B16A16_UINT 0x83 +#define GEN6_FORMAT_R16G16B16A16_FLOAT 0x84 +#define GEN6_FORMAT_R32G32_FLOAT 0x85 +#define GEN6_FORMAT_R32G32_SINT 0x86 +#define GEN6_FORMAT_R32G32_UINT 0x87 +#define GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS 0x88 +#define GEN6_FORMAT_X32_TYPELESS_G8X24_UINT 0x89 +#define GEN6_FORMAT_L32A32_FLOAT 0x8a +#define GEN6_FORMAT_R32G32_UNORM 0x8b +#define GEN6_FORMAT_R32G32_SNORM 0x8c +#define GEN6_FORMAT_R64_FLOAT 0x8d +#define GEN6_FORMAT_R16G16B16X16_UNORM 0x8e +#define GEN6_FORMAT_R16G16B16X16_FLOAT 0x8f +#define GEN6_FORMAT_A32X32_FLOAT 0x90 +#define GEN6_FORMAT_L32X32_FLOAT 0x91 +#define GEN6_FORMAT_I32X32_FLOAT 0x92 +#define GEN6_FORMAT_R16G16B16A16_SSCALED 0x93 +#define GEN6_FORMAT_R16G16B16A16_USCALED 0x94 +#define GEN6_FORMAT_R32G32_SSCALED 0x95 +#define GEN6_FORMAT_R32G32_USCALED 0x96 +#define GEN6_FORMAT_R32G32_SFIXED 0xa0 +#define GEN6_FORMAT_R64_PASSTHRU 0xa1 +#define GEN6_FORMAT_B8G8R8A8_UNORM 0xc0 +#define GEN6_FORMAT_B8G8R8A8_UNORM_SRGB 0xc1 +#define GEN6_FORMAT_R10G10B10A2_UNORM 0xc2 +#define GEN6_FORMAT_R10G10B10A2_UNORM_SRGB 0xc3 +#define GEN6_FORMAT_R10G10B10A2_UINT 0xc4 +#define GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM 0xc5 +#define GEN6_FORMAT_R8G8B8A8_UNORM 0xc7 +#define GEN6_FORMAT_R8G8B8A8_UNORM_SRGB 0xc8 +#define GEN6_FORMAT_R8G8B8A8_SNORM 0xc9 +#define GEN6_FORMAT_R8G8B8A8_SINT 0xca +#define GEN6_FORMAT_R8G8B8A8_UINT 0xcb +#define GEN6_FORMAT_R16G16_UNORM 0xcc +#define GEN6_FORMAT_R16G16_SNORM 0xcd +#define GEN6_FORMAT_R16G16_SINT 0xce +#define GEN6_FORMAT_R16G16_UINT 0xcf +#define GEN6_FORMAT_R16G16_FLOAT 0xd0 +#define GEN6_FORMAT_B10G10R10A2_UNORM 0xd1 +#define GEN6_FORMAT_B10G10R10A2_UNORM_SRGB 0xd2 +#define GEN6_FORMAT_R11G11B10_FLOAT 0xd3 +#define GEN6_FORMAT_R32_SINT 0xd6 +#define GEN6_FORMAT_R32_UINT 0xd7 +#define GEN6_FORMAT_R32_FLOAT 0xd8 +#define GEN6_FORMAT_R24_UNORM_X8_TYPELESS 0xd9 +#define GEN6_FORMAT_X24_TYPELESS_G8_UINT 0xda +#define GEN6_FORMAT_L32_UNORM 0xdd +#define GEN6_FORMAT_A32_UNORM 0xde +#define GEN6_FORMAT_L16A16_UNORM 0xdf +#define GEN6_FORMAT_I24X8_UNORM 0xe0 +#define GEN6_FORMAT_L24X8_UNORM 0xe1 +#define GEN6_FORMAT_A24X8_UNORM 0xe2 +#define GEN6_FORMAT_I32_FLOAT 0xe3 +#define GEN6_FORMAT_L32_FLOAT 0xe4 +#define GEN6_FORMAT_A32_FLOAT 0xe5 +#define GEN6_FORMAT_X8B8_UNORM_G8R8_SNORM 0xe6 +#define GEN6_FORMAT_A8X8_UNORM_G8R8_SNORM 0xe7 +#define GEN6_FORMAT_B8X8_UNORM_G8R8_SNORM 0xe8 +#define GEN6_FORMAT_B8G8R8X8_UNORM 0xe9 +#define GEN6_FORMAT_B8G8R8X8_UNORM_SRGB 0xea +#define GEN6_FORMAT_R8G8B8X8_UNORM 0xeb +#define GEN6_FORMAT_R8G8B8X8_UNORM_SRGB 0xec +#define GEN6_FORMAT_R9G9B9E5_SHAREDEXP 0xed +#define GEN6_FORMAT_B10G10R10X2_UNORM 0xee +#define GEN6_FORMAT_L16A16_FLOAT 0xf0 +#define GEN6_FORMAT_R32_UNORM 0xf1 +#define GEN6_FORMAT_R32_SNORM 0xf2 +#define GEN6_FORMAT_R10G10B10X2_USCALED 0xf3 +#define GEN6_FORMAT_R8G8B8A8_SSCALED 0xf4 +#define GEN6_FORMAT_R8G8B8A8_USCALED 0xf5 +#define GEN6_FORMAT_R16G16_SSCALED 0xf6 +#define GEN6_FORMAT_R16G16_USCALED 0xf7 +#define GEN6_FORMAT_R32_SSCALED 0xf8 +#define GEN6_FORMAT_R32_USCALED 0xf9 +#define GEN6_FORMAT_B5G6R5_UNORM 0x100 +#define GEN6_FORMAT_B5G6R5_UNORM_SRGB 0x101 +#define GEN6_FORMAT_B5G5R5A1_UNORM 0x102 +#define GEN6_FORMAT_B5G5R5A1_UNORM_SRGB 0x103 +#define GEN6_FORMAT_B4G4R4A4_UNORM 0x104 +#define GEN6_FORMAT_B4G4R4A4_UNORM_SRGB 0x105 +#define GEN6_FORMAT_R8G8_UNORM 0x106 +#define GEN6_FORMAT_R8G8_SNORM 0x107 +#define GEN6_FORMAT_R8G8_SINT 0x108 +#define GEN6_FORMAT_R8G8_UINT 0x109 +#define GEN6_FORMAT_R16_UNORM 0x10a +#define GEN6_FORMAT_R16_SNORM 0x10b +#define GEN6_FORMAT_R16_SINT 0x10c +#define GEN6_FORMAT_R16_UINT 0x10d +#define GEN6_FORMAT_R16_FLOAT 0x10e +#define GEN6_FORMAT_A8P8_UNORM_PALETTE0 0x10f +#define GEN6_FORMAT_A8P8_UNORM_PALETTE1 0x110 +#define GEN6_FORMAT_I16_UNORM 0x111 +#define GEN6_FORMAT_L16_UNORM 0x112 +#define GEN6_FORMAT_A16_UNORM 0x113 +#define GEN6_FORMAT_L8A8_UNORM 0x114 +#define GEN6_FORMAT_I16_FLOAT 0x115 +#define GEN6_FORMAT_L16_FLOAT 0x116 +#define GEN6_FORMAT_A16_FLOAT 0x117 +#define GEN6_FORMAT_L8A8_UNORM_SRGB 0x118 +#define GEN6_FORMAT_R5G5_SNORM_B6_UNORM 0x119 +#define GEN6_FORMAT_B5G5R5X1_UNORM 0x11a +#define GEN6_FORMAT_B5G5R5X1_UNORM_SRGB 0x11b +#define GEN6_FORMAT_R8G8_SSCALED 0x11c +#define GEN6_FORMAT_R8G8_USCALED 0x11d +#define GEN6_FORMAT_R16_SSCALED 0x11e +#define GEN6_FORMAT_R16_USCALED 0x11f +#define GEN6_FORMAT_P8A8_UNORM_PALETTE0 0x122 +#define GEN6_FORMAT_P8A8_UNORM_PALETTE1 0x123 +#define GEN6_FORMAT_A1B5G5R5_UNORM 0x124 +#define GEN6_FORMAT_A4B4G4R4_UNORM 0x125 +#define GEN6_FORMAT_L8A8_UINT 0x126 +#define GEN6_FORMAT_L8A8_SINT 0x127 +#define GEN6_FORMAT_R8_UNORM 0x140 +#define GEN6_FORMAT_R8_SNORM 0x141 +#define GEN6_FORMAT_R8_SINT 0x142 +#define GEN6_FORMAT_R8_UINT 0x143 +#define GEN6_FORMAT_A8_UNORM 0x144 +#define GEN6_FORMAT_I8_UNORM 0x145 +#define GEN6_FORMAT_L8_UNORM 0x146 +#define GEN6_FORMAT_P4A4_UNORM_PALETTE0 0x147 +#define GEN6_FORMAT_A4P4_UNORM_PALETTE0 0x148 +#define GEN6_FORMAT_R8_SSCALED 0x149 +#define GEN6_FORMAT_R8_USCALED 0x14a +#define GEN6_FORMAT_P8_UNORM_PALETTE0 0x14b +#define GEN6_FORMAT_L8_UNORM_SRGB 0x14c +#define GEN6_FORMAT_P8_UNORM_PALETTE1 0x14d +#define GEN6_FORMAT_P4A4_UNORM_PALETTE1 0x14e +#define GEN6_FORMAT_A4P4_UNORM_PALETTE1 0x14f +#define GEN6_FORMAT_Y8_UNORM 0x150 +#define GEN6_FORMAT_L8_UINT 0x152 +#define GEN6_FORMAT_L8_SINT 0x153 +#define GEN6_FORMAT_I8_UINT 0x154 +#define GEN6_FORMAT_I8_SINT 0x155 +#define GEN6_FORMAT_DXT1_RGB_SRGB 0x180 +#define GEN6_FORMAT_R1_UNORM 0x181 +#define GEN6_FORMAT_YCRCB_NORMAL 0x182 +#define GEN6_FORMAT_YCRCB_SWAPUVY 0x183 +#define GEN6_FORMAT_P2_UNORM_PALETTE0 0x184 +#define GEN6_FORMAT_P2_UNORM_PALETTE1 0x185 +#define GEN6_FORMAT_BC1_UNORM 0x186 +#define GEN6_FORMAT_BC2_UNORM 0x187 +#define GEN6_FORMAT_BC3_UNORM 0x188 +#define GEN6_FORMAT_BC4_UNORM 0x189 +#define GEN6_FORMAT_BC5_UNORM 0x18a +#define GEN6_FORMAT_BC1_UNORM_SRGB 0x18b +#define GEN6_FORMAT_BC2_UNORM_SRGB 0x18c +#define GEN6_FORMAT_BC3_UNORM_SRGB 0x18d +#define GEN6_FORMAT_MONO8 0x18e +#define GEN6_FORMAT_YCRCB_SWAPUV 0x18f +#define GEN6_FORMAT_YCRCB_SWAPY 0x190 +#define GEN6_FORMAT_DXT1_RGB 0x191 +#define GEN6_FORMAT_FXT1 0x192 +#define GEN6_FORMAT_R8G8B8_UNORM 0x193 +#define GEN6_FORMAT_R8G8B8_SNORM 0x194 +#define GEN6_FORMAT_R8G8B8_SSCALED 0x195 +#define GEN6_FORMAT_R8G8B8_USCALED 0x196 +#define GEN6_FORMAT_R64G64B64A64_FLOAT 0x197 +#define GEN6_FORMAT_R64G64B64_FLOAT 0x198 +#define GEN6_FORMAT_BC4_SNORM 0x199 +#define GEN6_FORMAT_BC5_SNORM 0x19a +#define GEN6_FORMAT_R16G16B16_FLOAT 0x19b +#define GEN6_FORMAT_R16G16B16_UNORM 0x19c +#define GEN6_FORMAT_R16G16B16_SNORM 0x19d +#define GEN6_FORMAT_R16G16B16_SSCALED 0x19e +#define GEN6_FORMAT_R16G16B16_USCALED 0x19f +#define GEN6_FORMAT_BC6H_SF16 0x1a1 +#define GEN6_FORMAT_BC7_UNORM 0x1a2 +#define GEN6_FORMAT_BC7_UNORM_SRGB 0x1a3 +#define GEN6_FORMAT_BC6H_UF16 0x1a4 +#define GEN6_FORMAT_PLANAR_420_8 0x1a5 +#define GEN6_FORMAT_R8G8B8_UNORM_SRGB 0x1a8 +#define GEN6_FORMAT_ETC1_RGB8 0x1a9 +#define GEN6_FORMAT_ETC2_RGB8 0x1aa +#define GEN6_FORMAT_EAC_R11 0x1ab +#define GEN6_FORMAT_EAC_RG11 0x1ac +#define GEN6_FORMAT_EAC_SIGNED_R11 0x1ad +#define GEN6_FORMAT_EAC_SIGNED_RG11 0x1ae +#define GEN6_FORMAT_ETC2_SRGB8 0x1af +#define GEN6_FORMAT_R16G16B16_UINT 0x1b0 +#define GEN6_FORMAT_R16G16B16_SINT 0x1b1 +#define GEN6_FORMAT_R32_SFIXED 0x1b2 +#define GEN6_FORMAT_R10G10B10A2_SNORM 0x1b3 +#define GEN6_FORMAT_R10G10B10A2_USCALED 0x1b4 +#define GEN6_FORMAT_R10G10B10A2_SSCALED 0x1b5 +#define GEN6_FORMAT_R10G10B10A2_SINT 0x1b6 +#define GEN6_FORMAT_B10G10R10A2_SNORM 0x1b7 +#define GEN6_FORMAT_B10G10R10A2_USCALED 0x1b8 +#define GEN6_FORMAT_B10G10R10A2_SSCALED 0x1b9 +#define GEN6_FORMAT_B10G10R10A2_UINT 0x1ba +#define GEN6_FORMAT_B10G10R10A2_SINT 0x1bb +#define GEN6_FORMAT_R64G64B64A64_PASSTHRU 0x1bc +#define GEN6_FORMAT_R64G64B64_PASSTHRU 0x1bd +#define GEN6_FORMAT_ETC2_RGB8_PTA 0x1c0 +#define GEN6_FORMAT_ETC2_SRGB8_PTA 0x1c1 +#define GEN6_FORMAT_ETC2_EAC_RGBA8 0x1c2 +#define GEN6_FORMAT_ETC2_EAC_SRGB8_A8 0x1c3 +#define GEN6_FORMAT_R8G8B8_UINT 0x1c8 +#define GEN6_FORMAT_R8G8B8_SINT 0x1c9 +#define GEN6_FORMAT_RAW 0x1ff +#define GEN6_SURFTYPE_1D 0x0 +#define GEN6_SURFTYPE_2D 0x1 +#define GEN6_SURFTYPE_3D 0x2 +#define GEN6_SURFTYPE_CUBE 0x3 +#define GEN6_SURFTYPE_BUFFER 0x4 +#define GEN7_SURFTYPE_STRBUF 0x5 +#define GEN6_SURFTYPE_NULL 0x7 +#define GEN6_TILING_NONE 0x0 +#define GEN6_TILING_X 0x2 +#define GEN6_TILING_Y 0x3 +#define GEN7_CLEAR_COLOR_ZERO 0x0 +#define GEN7_CLEAR_COLOR_ONE 0x1 +#define GEN75_SCS_ZERO 0x0 +#define GEN75_SCS_ONE 0x1 +#define GEN75_SCS_RED 0x4 +#define GEN75_SCS_GREEN 0x5 +#define GEN75_SCS_BLUE 0x6 +#define GEN75_SCS_ALPHA 0x7 +#define GEN6_MOCS_LLC__MASK 0x00000003 +#define GEN6_MOCS_LLC__SHIFT 0 +#define GEN6_MOCS_LLC_PTE 0x0 +#define GEN6_MOCS_LLC_UC 0x1 +#define GEN6_MOCS_LLC_ON 0x2 +#define GEN7_MOCS_LLC__MASK 0x00000002 +#define GEN7_MOCS_LLC__SHIFT 1 +#define GEN7_MOCS_LLC_PTE (0x0 << 1) +#define GEN7_MOCS_LLC_ON (0x1 << 1) +#define GEN75_MOCS_LLC__MASK 0x00000006 +#define GEN75_MOCS_LLC__SHIFT 1 +#define GEN75_MOCS_LLC_PTE (0x0 << 1) +#define GEN75_MOCS_LLC_UC (0x1 << 1) +#define GEN75_MOCS_LLC_ON (0x2 << 1) +#define GEN75_MOCS_LLC_ELLC (0x3 << 1) +#define GEN7_MOCS_L3__MASK 0x00000001 +#define GEN7_MOCS_L3__SHIFT 0 +#define GEN7_MOCS_L3_UC 0x0 +#define GEN7_MOCS_L3_ON 0x1 +#define GEN6_SURFACE_STATE__SIZE 8 + +#define GEN6_SURFACE_DW0_TYPE__MASK 0xe0000000 +#define GEN6_SURFACE_DW0_TYPE__SHIFT 29 +#define GEN6_SURFACE_DW0_FORMAT__MASK 0x07fc0000 +#define GEN6_SURFACE_DW0_FORMAT__SHIFT 18 +#define GEN6_SURFACE_DW0_VSTRIDE (0x1 << 12) +#define GEN6_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 11) +#define GEN6_SURFACE_DW0_MIPLAYOUT__MASK 0x00000400 +#define GEN6_SURFACE_DW0_MIPLAYOUT__SHIFT 10 +#define GEN6_SURFACE_DW0_MIPLAYOUT_BELOW (0x0 << 10) +#define GEN6_SURFACE_DW0_MIPLAYOUT_RIGHT (0x1 << 10) +#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE (0x1 << 9) +#define GEN6_SURFACE_DW0_RENDER_CACHE_RW (0x1 << 8) +#define GEN6_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK 0x000000c0 +#define GEN6_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT 6 +#define GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK 0x0000003f +#define GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__SHIFT 0 + + +#define GEN6_SURFACE_DW2_HEIGHT__MASK 0xfff80000 +#define GEN6_SURFACE_DW2_HEIGHT__SHIFT 19 +#define GEN6_SURFACE_DW2_WIDTH__MASK 0x0007ffc0 +#define GEN6_SURFACE_DW2_WIDTH__SHIFT 6 +#define GEN6_SURFACE_DW2_MIP_COUNT_LOD__MASK 0x0000003c +#define GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT 2 +#define GEN6_SURFACE_DW2_RTROTATE__MASK 0x00000003 +#define GEN6_SURFACE_DW2_RTROTATE__SHIFT 0 +#define GEN6_SURFACE_DW2_RTROTATE_0DEG 0x0 +#define GEN6_SURFACE_DW2_RTROTATE_90DEG 0x1 +#define GEN6_SURFACE_DW2_RTROTATE_270DEG 0x3 + +#define GEN6_SURFACE_DW3_DEPTH__MASK 0xffe00000 +#define GEN6_SURFACE_DW3_DEPTH__SHIFT 21 +#define GEN6_SURFACE_DW3_PITCH__MASK 0x000ffff8 +#define GEN6_SURFACE_DW3_PITCH__SHIFT 3 +#define GEN6_SURFACE_DW3_TILING__MASK 0x00000003 +#define GEN6_SURFACE_DW3_TILING__SHIFT 0 + +#define GEN6_SURFACE_DW4_MIN_LOD__MASK 0xf0000000 +#define GEN6_SURFACE_DW4_MIN_LOD__SHIFT 28 +#define GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK 0x0ffe0000 +#define GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT 17 +#define GEN6_SURFACE_DW4_RT_VIEW_EXTENT__MASK 0x0001ff00 +#define GEN6_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT 8 +#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT__MASK 0x00000070 +#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT 4 +#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT_1 (0x0 << 4) +#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT_4 (0x2 << 4) +#define GEN6_SURFACE_DW4_MSPOS_INDEX__MASK 0x00000007 +#define GEN6_SURFACE_DW4_MSPOS_INDEX__SHIFT 0 + +#define GEN6_SURFACE_DW5_X_OFFSET__MASK 0xfe000000 +#define GEN6_SURFACE_DW5_X_OFFSET__SHIFT 25 +#define GEN6_SURFACE_DW5_VALIGN__MASK 0x01000000 +#define GEN6_SURFACE_DW5_VALIGN__SHIFT 24 +#define GEN6_SURFACE_DW5_VALIGN_2 (0x0 << 24) +#define GEN6_SURFACE_DW5_VALIGN_4 (0x1 << 24) +#define GEN6_SURFACE_DW5_Y_OFFSET__MASK 0x00f00000 +#define GEN6_SURFACE_DW5_Y_OFFSET__SHIFT 20 +#define GEN6_SURFACE_DW5_MOCS__MASK 0x000f0000 +#define GEN6_SURFACE_DW5_MOCS__SHIFT 16 + + +#define GEN7_SURFACE_DW0_TYPE__MASK 0xe0000000 +#define GEN7_SURFACE_DW0_TYPE__SHIFT 29 +#define GEN7_SURFACE_DW0_IS_ARRAY (0x1 << 28) +#define GEN7_SURFACE_DW0_FORMAT__MASK 0x07fc0000 +#define GEN7_SURFACE_DW0_FORMAT__SHIFT 18 +#define GEN7_SURFACE_DW0_VALIGN__MASK 0x00030000 +#define GEN7_SURFACE_DW0_VALIGN__SHIFT 16 +#define GEN7_SURFACE_DW0_VALIGN_2 (0x0 << 16) +#define GEN7_SURFACE_DW0_VALIGN_4 (0x1 << 16) +#define GEN7_SURFACE_DW0_HALIGN__MASK 0x00008000 +#define GEN7_SURFACE_DW0_HALIGN__SHIFT 15 +#define GEN7_SURFACE_DW0_HALIGN_4 (0x0 << 15) +#define GEN7_SURFACE_DW0_HALIGN_8 (0x1 << 15) +#define GEN7_SURFACE_DW0_TILING__MASK 0x00006000 +#define GEN7_SURFACE_DW0_TILING__SHIFT 13 +#define GEN7_SURFACE_DW0_VSTRIDE (0x1 << 12) +#define GEN7_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 11) +#define GEN7_SURFACE_DW0_ARYSPC__MASK 0x00000400 +#define GEN7_SURFACE_DW0_ARYSPC__SHIFT 10 +#define GEN7_SURFACE_DW0_ARYSPC_FULL (0x0 << 10) +#define GEN7_SURFACE_DW0_ARYSPC_LOD0 (0x1 << 10) +#define GEN7_SURFACE_DW0_RENDER_CACHE_RW (0x1 << 8) +#define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK 0x000000c0 +#define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT 6 +#define GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK 0x0000003f +#define GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__SHIFT 0 + + +#define GEN7_SURFACE_DW2_HEIGHT__MASK 0x3fff0000 +#define GEN7_SURFACE_DW2_HEIGHT__SHIFT 16 +#define GEN7_SURFACE_DW2_WIDTH__MASK 0x00003fff +#define GEN7_SURFACE_DW2_WIDTH__SHIFT 0 + +#define GEN7_SURFACE_DW3_DEPTH__MASK 0xffe00000 +#define GEN7_SURFACE_DW3_DEPTH__SHIFT 21 +#define GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__MASK 0x001c0000 +#define GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__SHIFT 18 +#define GEN7_SURFACE_DW3_PITCH__MASK 0x0003ffff +#define GEN7_SURFACE_DW3_PITCH__SHIFT 0 + +#define GEN7_SURFACE_DW4_RTROTATE__MASK 0x60000000 +#define GEN7_SURFACE_DW4_RTROTATE__SHIFT 29 +#define GEN7_SURFACE_DW4_RTROTATE_0DEG (0x0 << 29) +#define GEN7_SURFACE_DW4_RTROTATE_90DEG (0x1 << 29) +#define GEN7_SURFACE_DW4_RTROTATE_270DEG (0x3 << 29) +#define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK 0x1ffc0000 +#define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT 18 +#define GEN7_SURFACE_DW4_RT_VIEW_EXTENT__MASK 0x0003ff80 +#define GEN7_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT 7 +#define GEN7_SURFACE_DW4_MSFMT__MASK 0x00000040 +#define GEN7_SURFACE_DW4_MSFMT__SHIFT 6 +#define GEN7_SURFACE_DW4_MSFMT_MSS (0x0 << 6) +#define GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL (0x1 << 6) +#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT__MASK 0x00000038 +#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT 3 +#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1 (0x0 << 3) +#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4 (0x2 << 3) +#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8 (0x3 << 3) +#define GEN7_SURFACE_DW4_MSPOS_INDEX__MASK 0x00000007 +#define GEN7_SURFACE_DW4_MSPOS_INDEX__SHIFT 0 + +#define GEN7_SURFACE_DW5_X_OFFSET__MASK 0xfe000000 +#define GEN7_SURFACE_DW5_X_OFFSET__SHIFT 25 +#define GEN7_SURFACE_DW5_Y_OFFSET__MASK 0x00f00000 +#define GEN7_SURFACE_DW5_Y_OFFSET__SHIFT 20 +#define GEN7_SURFACE_DW5_MOCS__MASK 0x000f0000 +#define GEN7_SURFACE_DW5_MOCS__SHIFT 16 +#define GEN7_SURFACE_DW5_MIN_LOD__MASK 0x000000f0 +#define GEN7_SURFACE_DW5_MIN_LOD__SHIFT 4 +#define GEN7_SURFACE_DW5_MIP_COUNT_LOD__MASK 0x0000000f +#define GEN7_SURFACE_DW5_MIP_COUNT_LOD__SHIFT 0 + +#define GEN7_SURFACE_DW6_UV_X_OFFSET__MASK 0x3fff0000 +#define GEN7_SURFACE_DW6_UV_X_OFFSET__SHIFT 16 +#define GEN7_SURFACE_DW6_UV_Y_OFFSET__MASK 0x00003fff +#define GEN7_SURFACE_DW6_UV_Y_OFFSET__SHIFT 0 +#define GEN7_SURFACE_DW6_MCS_ADDR__MASK 0xfffff000 +#define GEN7_SURFACE_DW6_MCS_ADDR__SHIFT 12 +#define GEN7_SURFACE_DW6_MCS_ADDR__SHR 12 +#define GEN7_SURFACE_DW6_MCS_PITCH__MASK 0x00000ff8 +#define GEN7_SURFACE_DW6_MCS_PITCH__SHIFT 3 +#define GEN7_SURFACE_DW6_MCS_ENABLE (0x1 << 0) +#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__MASK 0xffffffc0 +#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHIFT 6 +#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHR 6 +#define GEN7_SURFACE_DW6_APPEND_COUNTER_ENABLE (0x1 << 1) + +#define GEN7_SURFACE_DW7_CC_R__MASK 0x80000000 +#define GEN7_SURFACE_DW7_CC_R__SHIFT 31 +#define GEN7_SURFACE_DW7_CC_G__MASK 0x40000000 +#define GEN7_SURFACE_DW7_CC_G__SHIFT 30 +#define GEN7_SURFACE_DW7_CC_B__MASK 0x20000000 +#define GEN7_SURFACE_DW7_CC_B__SHIFT 29 +#define GEN7_SURFACE_DW7_CC_A__MASK 0x10000000 +#define GEN7_SURFACE_DW7_CC_A__SHIFT 28 +#define GEN75_SURFACE_DW7_SCS_R__MASK 0x0e000000 +#define GEN75_SURFACE_DW7_SCS_R__SHIFT 25 +#define GEN75_SURFACE_DW7_SCS_G__MASK 0x01c00000 +#define GEN75_SURFACE_DW7_SCS_G__SHIFT 22 +#define GEN75_SURFACE_DW7_SCS_B__MASK 0x00380000 +#define GEN75_SURFACE_DW7_SCS_B__SHIFT 19 +#define GEN75_SURFACE_DW7_SCS_A__MASK 0x00070000 +#define GEN75_SURFACE_DW7_SCS_A__SHIFT 16 +#define GEN7_SURFACE_DW7_RES_MIN_LOD__MASK 0x00000fff +#define GEN7_SURFACE_DW7_RES_MIN_LOD__SHIFT 0 + +#define GEN6_BINDING_TABLE_STATE__SIZE 256 + +#define GEN6_BINDING_TABLE_SURFACE_ADDR__MASK 0xffffffe0 +#define GEN6_BINDING_TABLE_SURFACE_ADDR__SHIFT 5 +#define GEN6_BINDING_TABLE_SURFACE_ADDR__SHR 5 + + +#endif /* GEN_RENDER_SURFACE_XML */ diff --git a/src/gallium/drivers/ilo/genhw/genhw.h b/src/gallium/drivers/ilo/genhw/genhw.h new file mode 100644 index 00000000000..b358433ce23 --- /dev/null +++ b/src/gallium/drivers/ilo/genhw/genhw.h @@ -0,0 +1,200 @@ +/* + * Mesa 3-D graphics library + * + * Copyright (C) 2014 LunarG, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GENHW_H +#define GENHW_H + +#include "pipe/p_compiler.h" +#include "util/u_debug.h" + +#include "intel_reg.h" +#include "brw_defines.h" + +#include "gen_regs.xml.h" +#include "gen_mi.xml.h" +#include "gen_blitter.xml.h" +#include "gen_render_surface.xml.h" +#include "gen_render_dynamic.xml.h" +#include "gen_render_3d.xml.h" +#include "gen_eu_isa.xml.h" +#include "gen_eu_message.xml.h" + +#define GEN_MI_CMD(op) (GEN6_MI_TYPE_MI | GEN6_MI_OPCODE_ ## op) + +#define GEN_BLITTER_CMD(op) \ + (GEN6_BLITTER_TYPE_BLITTER | GEN6_BLITTER_OPCODE_ ## op) + +#define GEN_RENDER_CMD(subtype, op) \ + (GEN6_RENDER_TYPE_RENDER | \ + GEN6_RENDER_SUBTYPE_ ## subtype | \ + GEN6_RENDER_OPCODE_ ## op) + +static inline bool +gen_is_snb(int devid) +{ + return (devid == 0x0102 || /* GT1 desktop */ + devid == 0x0112 || /* GT2 desktop */ + devid == 0x0122 || /* GT2_PLUS desktop */ + devid == 0x0106 || /* GT1 mobile */ + devid == 0x0116 || /* GT2 mobile */ + devid == 0x0126 || /* GT2_PLUS mobile */ + devid == 0x010a); /* GT1 server */ +} + +static inline int +gen_get_snb_gt(int devid) +{ + assert(gen_is_snb(devid)); + return (devid & 0x30) ? 2 : 1; +} + +static inline bool +gen_is_ivb(int devid) +{ + return (devid == 0x0152 || /* GT1 desktop */ + devid == 0x0162 || /* GT2 desktop */ + devid == 0x0156 || /* GT1 mobile */ + devid == 0x0166 || /* GT2 mobile */ + devid == 0x015a || /* GT1 server */ + devid == 0x016a); /* GT2 server */ +} + +static inline int +gen_get_ivb_gt(int devid) +{ + assert(gen_is_ivb(devid)); + return (devid & 0x30) >> 4; +} + +static inline bool +gen_is_hsw(int devid) +{ + return (devid == 0x0402 || /* GT1 desktop */ + devid == 0x0412 || /* GT2 desktop */ + devid == 0x0422 || /* GT3 desktop */ + devid == 0x0406 || /* GT1 mobile */ + devid == 0x0416 || /* GT2 mobile */ + devid == 0x0426 || /* GT2 mobile */ + devid == 0x040a || /* GT1 server */ + devid == 0x041a || /* GT2 server */ + devid == 0x042a || /* GT3 server */ + devid == 0x040b || /* GT1 reserved */ + devid == 0x041b || /* GT2 reserved */ + devid == 0x042b || /* GT3 reserved */ + devid == 0x040e || /* GT1 reserved */ + devid == 0x041e || /* GT2 reserved */ + devid == 0x042e || /* GT3 reserved */ + devid == 0x0c02 || /* SDV */ + devid == 0x0c12 || + devid == 0x0c22 || + devid == 0x0c06 || + devid == 0x0c16 || + devid == 0x0c26 || + devid == 0x0c0a || + devid == 0x0c1a || + devid == 0x0c2a || + devid == 0x0c0b || + devid == 0x0c1b || + devid == 0x0c2b || + devid == 0x0c0e || + devid == 0x0c1e || + devid == 0x0c2e || + devid == 0x0a02 || /* ULT */ + devid == 0x0a12 || + devid == 0x0a22 || + devid == 0x0a06 || + devid == 0x0a16 || + devid == 0x0a26 || + devid == 0x0a0a || + devid == 0x0a1a || + devid == 0x0a2a || + devid == 0x0a0b || + devid == 0x0a1b || + devid == 0x0a2b || + devid == 0x0a0e || + devid == 0x0a1e || + devid == 0x0a2e || + devid == 0x0d02 || /* CRW */ + devid == 0x0d12 || + devid == 0x0d22 || + devid == 0x0d06 || + devid == 0x0d16 || + devid == 0x0d26 || + devid == 0x0d0a || + devid == 0x0d1a || + devid == 0x0d2a || + devid == 0x0d0b || + devid == 0x0d1b || + devid == 0x0d2b || + devid == 0x0d0e || + devid == 0x0d1e || + devid == 0x0d2e); +} + +static inline int +gen_get_hsw_gt(int devid) +{ + assert(gen_is_hsw(devid)); + return ((devid & 0x30) >> 4) + 1; +} + +static inline bool +gen_is_vlv(int devid) +{ + return (devid == 0x0f30 || + devid == 0x0f31 || + devid == 0x0f32 || + devid == 0x0f33 || + devid == 0x0157 || + devid == 0x0155); +} + +static inline bool +gen_is_atom(int devid) +{ + return gen_is_vlv(devid); +} + +static inline bool +gen_is_desktop(int devid) +{ + assert(!gen_is_atom(devid)); + return ((devid & 0xf) == 0x2); +} + +static inline bool +gen_is_mobile(int devid) +{ + assert(!gen_is_atom(devid)); + return ((devid & 0xf) == 0x6); +} + +static inline bool +gen_is_server(int devid) +{ + assert(!gen_is_atom(devid)); + return ((devid & 0xf) == 0xa); +} + +#endif /* GENHW_H */ diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c index 6cc5e039c8d..744666072eb 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c @@ -25,9 +25,9 @@ * Chia-I Wu <[email protected]> */ +#include "genhw/genhw.h" #include "util/u_dual_blend.h" #include "util/u_prim.h" -#include "intel_reg.h" #include "ilo_blitter.h" #include "ilo_3d.h" diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c index 5ed8b7e1e6a..1c99655d026 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c @@ -25,8 +25,8 @@ * Chia-I Wu <[email protected]> */ +#include "genhw/genhw.h" #include "util/u_dual_blend.h" -#include "intel_reg.h" #include "ilo_blitter.h" #include "ilo_context.h" diff --git a/src/gallium/drivers/ilo/ilo_blitter_blt.c b/src/gallium/drivers/ilo/ilo_blitter_blt.c index d383b58d0bd..57eaa902439 100644 --- a/src/gallium/drivers/ilo/ilo_blitter_blt.c +++ b/src/gallium/drivers/ilo/ilo_blitter_blt.c @@ -25,8 +25,8 @@ * Chia-I Wu <[email protected]> */ +#include "genhw/genhw.h" #include "util/u_pack_color.h" -#include "intel_reg.h" #include "ilo_3d.h" #include "ilo_context.h" diff --git a/src/gallium/drivers/ilo/ilo_context.c b/src/gallium/drivers/ilo/ilo_context.c index a01934c9154..2de0ed7b04c 100644 --- a/src/gallium/drivers/ilo/ilo_context.c +++ b/src/gallium/drivers/ilo/ilo_context.c @@ -26,7 +26,6 @@ */ #include "util/u_upload_mgr.h" -#include "intel_chipset.h" #include "ilo_3d.h" #include "ilo_blit.h" diff --git a/src/gallium/drivers/ilo/ilo_cp.c b/src/gallium/drivers/ilo/ilo_cp.c index 16871f971ec..af6c442e5d6 100644 --- a/src/gallium/drivers/ilo/ilo_cp.c +++ b/src/gallium/drivers/ilo/ilo_cp.c @@ -25,7 +25,7 @@ * Chia-I Wu <[email protected]> */ -#include "intel_reg.h" /* for MI_xxx */ +#include "genhw/genhw.h" /* for MI_xxx */ #include "intel_winsys.h" #include "ilo_cp.h" diff --git a/src/gallium/drivers/ilo/ilo_format.c b/src/gallium/drivers/ilo/ilo_format.c index 30e495837d5..a69f94d91a1 100644 --- a/src/gallium/drivers/ilo/ilo_format.c +++ b/src/gallium/drivers/ilo/ilo_format.c @@ -25,8 +25,8 @@ * Chia-I Wu <[email protected]> */ +#include "genhw/genhw.h" #include "vl/vl_video_buffer.h" -#include "brw_defines.h" #include "ilo_screen.h" #include "ilo_format.h" diff --git a/src/gallium/drivers/ilo/ilo_format.h b/src/gallium/drivers/ilo/ilo_format.h index 23dcbc550f3..1be3577774d 100644 --- a/src/gallium/drivers/ilo/ilo_format.h +++ b/src/gallium/drivers/ilo/ilo_format.h @@ -28,7 +28,7 @@ #ifndef ILO_FORMAT_H #define ILO_FORMAT_H -#include "brw_defines.h" +#include "genhw/genhw.h" #include "ilo_common.h" diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen6.c b/src/gallium/drivers/ilo/ilo_gpe_gen6.c index c4b8839d474..0e2cb0ebd54 100644 --- a/src/gallium/drivers/ilo/ilo_gpe_gen6.c +++ b/src/gallium/drivers/ilo/ilo_gpe_gen6.c @@ -25,11 +25,10 @@ * Chia-I Wu <[email protected]> */ +#include "genhw/genhw.h" #include "util/u_dual_blend.h" #include "util/u_framebuffer.h" #include "util/u_half.h" -#include "brw_defines.h" -#include "intel_reg.h" #include "ilo_context.h" #include "ilo_format.h" diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen6.h b/src/gallium/drivers/ilo/ilo_gpe_gen6.h index d14e5c6fab0..bbcbced4d66 100644 --- a/src/gallium/drivers/ilo/ilo_gpe_gen6.h +++ b/src/gallium/drivers/ilo/ilo_gpe_gen6.h @@ -28,8 +28,7 @@ #ifndef ILO_GPE_GEN6_H #define ILO_GPE_GEN6_H -#include "brw_defines.h" -#include "intel_reg.h" +#include "genhw/genhw.h" #include "intel_winsys.h" #include "ilo_common.h" diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen7.c b/src/gallium/drivers/ilo/ilo_gpe_gen7.c index e432975f94b..f5a32695140 100644 --- a/src/gallium/drivers/ilo/ilo_gpe_gen7.c +++ b/src/gallium/drivers/ilo/ilo_gpe_gen7.c @@ -25,9 +25,8 @@ * Chia-I Wu <[email protected]> */ +#include "genhw/genhw.h" #include "util/u_resource.h" -#include "brw_defines.h" -#include "intel_reg.h" #include "ilo_format.h" #include "ilo_resource.h" diff --git a/src/gallium/drivers/ilo/ilo_screen.c b/src/gallium/drivers/ilo/ilo_screen.c index 4bea564e6a0..8c2e04e220d 100644 --- a/src/gallium/drivers/ilo/ilo_screen.c +++ b/src/gallium/drivers/ilo/ilo_screen.c @@ -28,8 +28,7 @@ #include "util/u_format_s3tc.h" #include "vl/vl_decoder.h" #include "vl/vl_video_buffer.h" -#include "intel_chipset.h" -#include "intel_reg.h" /* for TIMESTAMP */ +#include "genhw/genhw.h" /* for TIMESTAMP */ #include "intel_winsys.h" #include "ilo_context.h" @@ -457,89 +456,39 @@ static const char * ilo_get_name(struct pipe_screen *screen) { struct ilo_screen *is = ilo_screen(screen); - const char *chipset; - - /* stolen from classic i965 */ - switch (is->dev.devid) { - case PCI_CHIP_SANDYBRIDGE_GT1: - case PCI_CHIP_SANDYBRIDGE_GT2: - case PCI_CHIP_SANDYBRIDGE_GT2_PLUS: - chipset = "Intel(R) Sandybridge Desktop"; - break; - case PCI_CHIP_SANDYBRIDGE_M_GT1: - case PCI_CHIP_SANDYBRIDGE_M_GT2: - case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS: - chipset = "Intel(R) Sandybridge Mobile"; - break; - case PCI_CHIP_SANDYBRIDGE_S: - chipset = "Intel(R) Sandybridge Server"; - break; - case PCI_CHIP_IVYBRIDGE_GT1: - case PCI_CHIP_IVYBRIDGE_GT2: - chipset = "Intel(R) Ivybridge Desktop"; - break; - case PCI_CHIP_IVYBRIDGE_M_GT1: - case PCI_CHIP_IVYBRIDGE_M_GT2: - chipset = "Intel(R) Ivybridge Mobile"; - break; - case PCI_CHIP_IVYBRIDGE_S_GT1: - case PCI_CHIP_IVYBRIDGE_S_GT2: - chipset = "Intel(R) Ivybridge Server"; - break; - case PCI_CHIP_BAYTRAIL_M_1: - case PCI_CHIP_BAYTRAIL_M_2: - case PCI_CHIP_BAYTRAIL_M_3: - case PCI_CHIP_BAYTRAIL_M_4: - case PCI_CHIP_BAYTRAIL_D: + const char *chipset = NULL; + + if (gen_is_vlv(is->dev.devid)) { chipset = "Intel(R) Bay Trail"; - break; - case PCI_CHIP_HASWELL_GT1: - case PCI_CHIP_HASWELL_GT2: - case PCI_CHIP_HASWELL_GT3: - case PCI_CHIP_HASWELL_SDV_GT1: - case PCI_CHIP_HASWELL_SDV_GT2: - case PCI_CHIP_HASWELL_SDV_GT3: - case PCI_CHIP_HASWELL_ULT_GT1: - case PCI_CHIP_HASWELL_ULT_GT2: - case PCI_CHIP_HASWELL_ULT_GT3: - case PCI_CHIP_HASWELL_CRW_GT1: - case PCI_CHIP_HASWELL_CRW_GT2: - case PCI_CHIP_HASWELL_CRW_GT3: - chipset = "Intel(R) Haswell Desktop"; - break; - case PCI_CHIP_HASWELL_M_GT1: - case PCI_CHIP_HASWELL_M_GT2: - case PCI_CHIP_HASWELL_M_GT3: - case PCI_CHIP_HASWELL_SDV_M_GT1: - case PCI_CHIP_HASWELL_SDV_M_GT2: - case PCI_CHIP_HASWELL_SDV_M_GT3: - case PCI_CHIP_HASWELL_ULT_M_GT1: - case PCI_CHIP_HASWELL_ULT_M_GT2: - case PCI_CHIP_HASWELL_ULT_M_GT3: - case PCI_CHIP_HASWELL_CRW_M_GT1: - case PCI_CHIP_HASWELL_CRW_M_GT2: - case PCI_CHIP_HASWELL_CRW_M_GT3: - chipset = "Intel(R) Haswell Mobile"; - break; - case PCI_CHIP_HASWELL_S_GT1: - case PCI_CHIP_HASWELL_S_GT2: - case PCI_CHIP_HASWELL_S_GT3: - case PCI_CHIP_HASWELL_SDV_S_GT1: - case PCI_CHIP_HASWELL_SDV_S_GT2: - case PCI_CHIP_HASWELL_SDV_S_GT3: - case PCI_CHIP_HASWELL_ULT_S_GT1: - case PCI_CHIP_HASWELL_ULT_S_GT2: - case PCI_CHIP_HASWELL_ULT_S_GT3: - case PCI_CHIP_HASWELL_CRW_S_GT1: - case PCI_CHIP_HASWELL_CRW_S_GT2: - case PCI_CHIP_HASWELL_CRW_S_GT3: - chipset = "Intel(R) Haswell Server"; - break; - default: - chipset = "Unknown Intel Chipset"; - break; + } + else if (gen_is_hsw(is->dev.devid)) { + if (gen_is_desktop(is->dev.devid)) + chipset = "Intel(R) Haswell Desktop"; + else if (gen_is_mobile(is->dev.devid)) + chipset = "Intel(R) Haswell Mobile"; + else if (gen_is_server(is->dev.devid)) + chipset = "Intel(R) Haswell Server"; + } + else if (gen_is_ivb(is->dev.devid)) { + if (gen_is_desktop(is->dev.devid)) + chipset = "Intel(R) Ivybridge Desktop"; + else if (gen_is_mobile(is->dev.devid)) + chipset = "Intel(R) Ivybridge Mobile"; + else if (gen_is_server(is->dev.devid)) + chipset = "Intel(R) Ivybridge Server"; + } + else if (gen_is_snb(is->dev.devid)) { + if (gen_is_desktop(is->dev.devid)) + chipset = "Intel(R) Sandybridge Desktop"; + else if (gen_is_mobile(is->dev.devid)) + chipset = "Intel(R) Sandybridge Mobile"; + else if (gen_is_server(is->dev.devid)) + chipset = "Intel(R) Sandybridge Server"; } + if (!chipset) + chipset = "Unknown Intel Chipset"; + return chipset; } @@ -698,45 +647,21 @@ init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info) * 256k 8096 4096" */ - if (IS_HASWELL(info->devid)) { + if (gen_is_hsw(info->devid)) { dev->gen = ILO_GEN(7.5); - - if (IS_HSW_GT3(info->devid)) { - dev->gt = 3; - dev->urb_size = 512 * 1024; - } - else if (IS_HSW_GT2(info->devid)) { - dev->gt = 2; - dev->urb_size = 256 * 1024; - } - else { - dev->gt = 1; - dev->urb_size = 128 * 1024; - } + dev->gt = gen_get_hsw_gt(info->devid); + dev->urb_size = ((dev->gt == 3) ? 512 : + (dev->gt == 2) ? 256 : 128) * 1024; } - else if (IS_GEN7(info->devid)) { + else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) { dev->gen = ILO_GEN(7); - - if (IS_IVB_GT2(info->devid)) { - dev->gt = 2; - dev->urb_size = 256 * 1024; - } - else { - dev->gt = 1; - dev->urb_size = 128 * 1024; - } + dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1; + dev->urb_size = ((dev->gt == 2) ? 256 : 128) * 1024; } - else if (IS_GEN6(info->devid)) { + else if (gen_is_snb(info->devid)) { dev->gen = ILO_GEN(6); - - if (IS_SNB_GT2(info->devid)) { - dev->gt = 2; - dev->urb_size = 64 * 1024; - } - else { - dev->gt = 1; - dev->urb_size = 32 * 1024; - } + dev->gt = gen_get_snb_gt(info->devid); + dev->urb_size = ((dev->gt == 2) ? 64 : 32) * 1024; } else { ilo_err("unknown GPU generation\n"); diff --git a/src/gallium/drivers/ilo/ilo_shader.c b/src/gallium/drivers/ilo/ilo_shader.c index 480b4771816..480166a89b4 100644 --- a/src/gallium/drivers/ilo/ilo_shader.c +++ b/src/gallium/drivers/ilo/ilo_shader.c @@ -25,9 +25,9 @@ * Chia-I Wu <[email protected]> */ +#include "genhw/genhw.h" /* for SBE setup */ #include "tgsi/tgsi_parse.h" #include "intel_winsys.h" -#include "brw_defines.h" /* for SBE setup */ #include "shader/ilo_shader_internal.h" #include "ilo_state.h" diff --git a/src/gallium/drivers/ilo/shader/toy_compiler.h b/src/gallium/drivers/ilo/shader/toy_compiler.h index cc5fc8079a6..372a2ac200d 100644 --- a/src/gallium/drivers/ilo/shader/toy_compiler.h +++ b/src/gallium/drivers/ilo/shader/toy_compiler.h @@ -28,8 +28,8 @@ #ifndef TOY_COMPILER_H #define TOY_COMPILER_H +#include "genhw/genhw.h" #include "util/u_slab.h" -#include "brw_defines.h" #include "ilo_common.h" #include "toy_compiler_reg.h" |