diff options
author | Jason Ekstrand <[email protected]> | 2016-11-12 07:56:41 -0800 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2016-11-16 10:08:36 -0800 |
commit | 0087064f26d94ded714b9d6231fdb815a9f3f9a1 (patch) | |
tree | c7aede8504e3e26afb29d08657815d3bddaec332 | |
parent | cd724208d3e1e3307f84a794f2c1fc83b69ccf8a (diff) |
anv/pipeline: Set correct binding table and sampler counts
Reviewed-by: Timothy Arceri <[email protected]>
Reviewed-by: Kristian H. Kristensen <[email protected]>
-rw-r--r-- | src/intel/vulkan/gen7_pipeline.c | 24 | ||||
-rw-r--r-- | src/intel/vulkan/gen8_pipeline.c | 21 | ||||
-rw-r--r-- | src/intel/vulkan/genX_pipeline_util.h | 12 |
3 files changed, 49 insertions, 8 deletions
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c index 4ffb16cb730..b54610c072c 100644 --- a/src/intel/vulkan/gen7_pipeline.c +++ b/src/intel/vulkan/gen7_pipeline.c @@ -106,9 +106,12 @@ genX(graphics_pipeline_create)( gen7_emit_vs_workaround_flush(brw); #endif - if (pipeline->vs_vec4 == NO_KERNEL) + if (pipeline->vs_vec4 == NO_KERNEL) { anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs); - else + } else { + const struct anv_shader_bin *vs_bin = + pipeline->shaders[MESA_SHADER_VERTEX]; + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) { vs.KernelStartPointer = pipeline->vs_vec4; @@ -123,18 +126,25 @@ genX(graphics_pipeline_create)( vs.DispatchGRFStartRegisterforURBData = vs_prog_data->base.base.dispatch_grf_start_reg; + vs.SamplerCount = get_sampler_count(vs_bin); + vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin); + vs.VertexURBEntryReadLength = vs_prog_data->base.urb_read_length; vs.VertexURBEntryReadOffset = 0; vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1; vs.StatisticsEnable = true; vs.VSFunctionEnable = true; } + } const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline); if (pipeline->gs_kernel == NO_KERNEL) { anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs); } else { + const struct anv_shader_bin *gs_bin = + pipeline->shaders[MESA_SHADER_GEOMETRY]; + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) { gs.KernelStartPointer = pipeline->gs_kernel; @@ -154,6 +164,9 @@ genX(graphics_pipeline_create)( gs.DispatchGRFStartRegisterforURBData = gs_prog_data->base.base.dispatch_grf_start_reg; + gs.SamplerCount = get_sampler_count(gs_bin); + gs.BindingTableEntryCount = get_binding_table_entry_count(gs_bin); + gs.MaximumNumberofThreads = devinfo->max_gs_threads - 1; /* This in the next dword on HSW. */ gs.ControlDataFormat = gs_prog_data->control_data_format; @@ -190,6 +203,9 @@ genX(graphics_pipeline_create)( ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1; } } else { + const struct anv_shader_bin *fs_bin = + pipeline->shaders[MESA_SHADER_FRAGMENT]; + const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline); if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 || wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1) @@ -211,6 +227,10 @@ genX(graphics_pipeline_create)( .offset = 0, }; ps.PerThreadScratchSpace = scratch_space(&wm_prog_data->base); + + ps.SamplerCount = get_sampler_count(fs_bin); + ps.BindingTableEntryCount = get_binding_table_entry_count(fs_bin); + ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1; ps.PushConstantEnable = wm_prog_data->base.nr_params > 0; ps.AttributeEnable = wm_prog_data->num_varying_inputs > 0; diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c index 6cf55f551b2..10cef64fcba 100644 --- a/src/intel/vulkan/gen8_pipeline.c +++ b/src/intel/vulkan/gen8_pipeline.c @@ -117,6 +117,9 @@ genX(graphics_pipeline_create)( anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs); } else { const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline); + const struct anv_shader_bin *gs_bin = + pipeline->shaders[MESA_SHADER_GEOMETRY]; + offset = 1; length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset; @@ -124,8 +127,8 @@ genX(graphics_pipeline_create)( gs.SingleProgramFlow = false; gs.KernelStartPointer = pipeline->gs_kernel; gs.VectorMaskEnable = false; - gs.SamplerCount = 0; - gs.BindingTableEntryCount = 0; + gs.SamplerCount = get_sampler_count(gs_bin); + gs.BindingTableEntryCount = get_binding_table_entry_count(gs_bin); gs.ExpectedVertexCount = gs_prog_data->vertices_in; gs.ScratchSpaceBasePointer = (struct anv_address) { @@ -186,14 +189,16 @@ genX(graphics_pipeline_create)( vs.VertexURBEntryOutputLength = length; } } else { + const struct anv_shader_bin *vs_bin = + pipeline->shaders[MESA_SHADER_VERTEX]; + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) { vs.KernelStartPointer = vs_start; vs.SingleVertexDispatch = false; vs.VectorMaskEnable = false; - vs.SamplerCount = 0; - vs.BindingTableEntryCount = - vs_prog_data->base.base.binding_table.size_bytes / 4; + vs.SamplerCount = get_sampler_count(vs_bin); + vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin); vs.ThreadDispatchPriority = false; vs.FloatingPointMode = IEEE754; @@ -237,6 +242,9 @@ genX(graphics_pipeline_create)( extra.PixelShaderValid = false; } } else { + const struct anv_shader_bin *fs_bin = + pipeline->shaders[MESA_SHADER_FRAGMENT]; + emit_3dstate_sbe(pipeline); anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) { @@ -248,7 +256,8 @@ genX(graphics_pipeline_create)( ps._32PixelDispatchEnable = false; ps.SingleProgramFlow = false; ps.VectorMaskEnable = true; - ps.SamplerCount = 1; + ps.SamplerCount = get_sampler_count(fs_bin); + ps.BindingTableEntryCount = get_binding_table_entry_count(fs_bin); ps.PushConstantEnable = wm_prog_data->base.nr_params > 0; ps.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ? POSOFFSET_SAMPLE: POSOFFSET_NONE; diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h index 129ae94aeba..b30be1443db 100644 --- a/src/intel/vulkan/genX_pipeline_util.h +++ b/src/intel/vulkan/genX_pipeline_util.h @@ -956,4 +956,16 @@ emit_3dstate_streamout(struct anv_pipeline *pipeline, } } +static inline uint32_t +get_sampler_count(const struct anv_shader_bin *bin) +{ + return DIV_ROUND_UP(bin->bind_map.sampler_count, 4); +} + +static inline uint32_t +get_binding_table_entry_count(const struct anv_shader_bin *bin) +{ + return DIV_ROUND_UP(bin->bind_map.surface_count, 32); +} + #endif /* GENX_PIPELINE_UTIL_H */ |