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authorDave Airlie <[email protected]>2010-09-20 10:34:42 +1000
committerDave Airlie <[email protected]>2010-09-20 10:35:38 +1000
commit4af55364ccb50e4f19cbb59ac6f51d86f58dedba (patch)
tree9f18649d65b20d93a6218c6ca7b16d5bf9fee7ba
parent3d12c207d7f9f1d25a0ee7f1bf94ce9a7f70dff3 (diff)
r600g: fix fbo-drawbuffers-maxtargets
we were leaking buffers since the flush code was added, it wasn't dropping references. move setting up flush to the set_framebuffer_state. clean up the flush state object. make more space in the BOs array for flushing.
-rw-r--r--src/gallium/drivers/r600/r600_state.c29
-rw-r--r--src/gallium/drivers/r600/radeon.h5
2 files changed, 26 insertions, 8 deletions
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 4dcdc492fc1..e347943873c 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -33,6 +33,10 @@
#include "r600_context.h"
#include "r600_resource.h"
+static void clean_flush(struct r600_context *rctx, struct radeon_state *flush);
+static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush);
+static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush);
+
static struct r600_context_state *r600_new_context_state(unsigned type)
{
struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
@@ -379,6 +383,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
int i;
r600_context_state_decref(rctx->framebuffer);
+ clean_flush(rctx, &rctx->hw_states.cb_flush);
+ clean_flush(rctx, &rctx->hw_states.db_flush);
rstate = r600_new_context_state(pipe_framebuffer_type);
rstate->state.framebuffer = *state;
@@ -393,6 +399,10 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
if (state->zsbuf) {
rctx->vtbl->db(rctx, &rstate->rstate[0], state);
}
+ /* setup flush states */
+ setup_cb_flush(rctx, &rctx->hw_states.cb_flush);
+ setup_db_flush(rctx, &rctx->hw_states.db_flush);
+
return;
}
@@ -554,6 +564,7 @@ struct r600_context_state *r600_context_state_decref(struct r600_context_state *
case pipe_framebuffer_type:
for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
+ radeon_state_fini(&rstate->rstate[i+1]);
}
pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
break;
@@ -600,6 +611,17 @@ static void r600_bind_shader_sampler(struct r600_context *rctx, struct r600_shad
}
}
+static void clean_flush(struct r600_context *rctx, struct radeon_state *flush)
+{
+ struct r600_screen *rscreen = rctx->screen;
+ int i;
+
+ for (i = 0 ; i < flush->nbo; i++) {
+ radeon_ws_bo_reference(rscreen->rw, &flush->bo[i], NULL);
+ }
+ flush->nbo = 0;
+ radeon_state_fini(flush);
+}
static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush)
{
@@ -658,10 +680,6 @@ int r600_context_hw_states(struct pipe_context *ctx)
rctx->vtbl->dsa(rctx, &rctx->hw_states.dsa);
rctx->vtbl->cb_cntl(rctx, &rctx->hw_states.cb_cntl);
- /* setup flushes */
- setup_db_flush(rctx, &rctx->hw_states.db_flush);
- setup_cb_flush(rctx, &rctx->hw_states.cb_flush);
-
/* bind states */
radeon_draw_bind(&rctx->draw, &rctx->config);
@@ -673,9 +691,6 @@ int r600_context_hw_states(struct pipe_context *ctx)
radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
- radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
- radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
-
if (rctx->viewport) {
radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
}
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 5249194eb19..06b5cec5a6e 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -102,6 +102,9 @@ void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
struct radeon_ws_bo *src);
struct radeon_stype_info;
+
+/* currently limited to max buffers in a cb flush */
+#define RADEON_STATE_MAX_BO 8
/*
* states functions
*/
@@ -119,7 +122,7 @@ struct radeon_state {
u32 pm4_crc;
u32 pm4[128];
unsigned nbo;
- struct radeon_ws_bo *bo[4];
+ struct radeon_ws_bo *bo[RADEON_STATE_MAX_BO];
unsigned nreloc;
unsigned reloc_pm4_id[8];
unsigned reloc_bo_id[8];