diff options
| author | Tom Stellard <[email protected]> | 2012-06-25 20:00:47 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-07-09 13:41:17 +0000 |
| commit | 38be0966c7e58fb3017c222cf416ae2bdc0bee3d (patch) | |
| tree | bbbcfc929a841d86cc1c8acbfbc9b28bff6dc351 | |
| parent | 7d0c17fe74ec0a264fb0441e6774f6708e940614 (diff) | |
r600g: Add pkt_flag member to struct r600_command_buffer
Some packets require the shader type bit (bit 1) to be set when
used for compute shaders. The pkt_flag will be initialized to
RADEON_CP_PACKET3_COMPUTE_MODE for any struct r600_command_buffer used
for dispatching compute shaders and it will be or'd against the result of
the PKT3 macro when adding a new packet to a struct r600_command buffer.
Reviewed-by: Marek Olšák <[email protected]>
| -rw-r--r-- | src/gallium/drivers/r600/r600_pipe.h | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 82c4a125024..cd67ee11e4e 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -68,6 +68,7 @@ struct r600_command_buffer { struct r600_atom atom; uint32_t *buf; unsigned max_num_dw; + unsigned pkt_flags; }; struct r600_surface_sync_cmd { @@ -584,19 +585,27 @@ static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, uns cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; } +/** + * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute + * shaders. + */ static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); + cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; } +/** + * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute + * shaders. + */ static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= R600_CTL_CONST_OFFSET); assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); + cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; } @@ -608,11 +617,15 @@ static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, uns cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; } +/** + * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute + * shaders. + */ static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= EG_LOOP_CONST_OFFSET); assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); + cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; } |