diff options
author | Eric Anholt <[email protected]> | 2011-06-05 23:20:57 -0700 |
---|---|---|
committer | Eric Anholt <[email protected]> | 2011-06-07 00:08:42 -0700 |
commit | ef59049c5242a1be7fa59a182d342191185dd62b (patch) | |
tree | 870dd5f8a53224fb65d2d236612b02a87fdbe778 | |
parent | 7d2cb9a53c288ddafdf9cfd1b3162bcbb903de96 (diff) |
i965: Fix flipped GT1 vs GT2 URB VS entry count limits.
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 0256ab9061f..d6a99ab06e2 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -203,12 +203,12 @@ GLboolean brwCreateContext( int api, brw->wm_max_threads = 40; brw->vs_max_threads = 60; brw->urb.size = 64; /* volume 5c.5 section 5.1 */ - brw->urb.max_vs_entries = 128; /* volume 2a (see 3DSTATE_URB) */ + brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */ } else { brw->wm_max_threads = 40; brw->vs_max_threads = 24; brw->urb.size = 32; /* volume 5c.5 section 5.1 */ - brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */ + brw->urb.max_vs_entries = 128; /* volume 2a (see 3DSTATE_URB) */ } } else if (intel->gen == 5) { brw->urb.size = 1024; |