diff options
| author | Kenneth Graunke <[email protected]> | 2011-09-24 00:42:23 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2012-03-30 14:39:03 -0700 |
| commit | b4410ac3944ee30bbf5455e3e649b73f559a7d38 (patch) | |
| tree | a99a79238e30bd25fde77c9a307b371a555ad014 | |
| parent | 1b3a199097190a0bf857eb17c12949fa2b456d9b (diff) | |
i965: Set Line Stipple enable bit in 3DSTATE_SF for Haswell.
Apparently this needs to be the same as in 3DSTATE_WM.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_sf_state.c | 3 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 41534b645f9..a0931121475 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1210,6 +1210,8 @@ enum brw_message_target { */ /* GEN7/DW1: */ # define GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT 12 +/* GEN7/DW2: */ +# define HSW_SF_LINE_STIPPLE_ENABLE 14 #define _3DSTATE_SBE 0x781F /* GEN7+ */ /* DW1 */ diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c index c8f4393a529..5c51abc5a0e 100644 --- a/src/mesa/drivers/dri/i965/gen7_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c @@ -249,6 +249,9 @@ upload_sf_state(struct brw_context *brw) dw2 |= GEN6_SF_LINE_AA_MODE_TRUE; dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0; } + if (ctx->Line.StippleFlag && intel->is_haswell) { + dw2 |= HSW_SF_LINE_STIPPLE_ENABLE; + } /* FINISHME: Last Pixel Enable? Vertex Sub Pixel Precision Select? * FINISHME: AA Line Distance Mode? |