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authorEric Anholt <[email protected]>2013-04-11 10:34:59 -0700
committerEric Anholt <[email protected]>2013-04-12 16:32:13 -0700
commit28170c5b7f1feaa5918f4f5427435b0ad53a8c2f (patch)
treec0391af33cf30fd0f6da2a73db082392c5d8df8b
parent248175ab3b90139580f7e9403ac5243d7aeac823 (diff)
i965: Fix an unused variable warning in the release build.
I think this actually clarifies what's going on in the asserts a bit, given how many regions we've got floating around. Reviewed-by: Matt Turner <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index db6bc2d8993..953f6cdbdb3 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -599,8 +599,6 @@ brw_emit_depthbuffer(struct brw_context *brw)
}
if (depth_irb) {
- struct intel_region *region = depth_mt->region;
-
/* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
* 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
* depthstencil format.
@@ -616,8 +614,8 @@ brw_emit_depthbuffer(struct brw_context *brw)
/* Prior to Gen7, if using separate stencil, hiz must be enabled. */
assert(intel->gen >= 7 || !separate_stencil || hiz);
- assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
- assert(!hiz || region->tiling == I915_TILING_Y);
+ assert(intel->gen < 6 || depth_mt->region->tiling == I915_TILING_Y);
+ assert(!hiz || depth_mt->region->tiling == I915_TILING_Y);
depthbuffer_format = brw_depthbuffer_format(brw);
depth_surface_type = BRW_SURFACE_2D;