diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2018-01-04 01:45:15 +0100 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2018-01-04 19:35:36 +0100 |
| commit | f2c9f13ec2fdab99f5aa7f32845ee94dd1942fe9 (patch) | |
| tree | c1db677846441749230540fcef1101c77d8b6dd9 | |
| parent | 2670ebb5840c2108c55607520f1cf9eb5868e27a (diff) | |
radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.
These are just shaders reads, so we need to invalidate L1.
Fixes: 6dbb0eaccc "radv: handle subpass cache flushes"
Reviewed-by: Samuel Pitoiset <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 6dc80acef07..0faf8030b49 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2014,11 +2014,11 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, switch ((VkAccessFlagBits)(1 << b)) { case VK_ACCESS_INDIRECT_COMMAND_READ_BIT: case VK_ACCESS_INDEX_READ_BIT: - case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT: break; case VK_ACCESS_UNIFORM_READ_BIT: flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1; break; + case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT: case VK_ACCESS_SHADER_READ_BIT: case VK_ACCESS_TRANSFER_READ_BIT: case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT: |