diff options
| author | Lionel Landwerlin <[email protected]> | 2019-04-18 12:00:08 +0100 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2019-04-18 17:43:08 +0100 |
| commit | eaadb62c9ea98f841d7ffc26c14341abdf84d2d6 (patch) | |
| tree | 0cd0ca5889ecbff0b95eab27583b50ca1bd16ac5 | |
| parent | d1be67db39463b48369cb71979ed18662b2c157e (diff) | |
i965: implement WaEnableStateCacheRedirectToCS
This 3d performance workaround was initially put in the kernel but the
media driver requires different settings so the register has been
whitelisted in i915 [1] and userspace drivers are left initializing it as
they wish.
[1] : https://patchwork.freedesktop.org/series/59494/
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Anuj Phogat <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index d9ea1057123..17bca1991f1 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1674,6 +1674,7 @@ enum brw_pixel_shader_coverage_mask_mode { # define GLK_SCEC_BARRIER_MODE_GPGPU (0 << 7) # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7) # define GLK_SCEC_BARRIER_MODE_MASK REG_MASK(1 << 7) +# define GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE (1 << 11) #define COMMON_SLICE_CHICKEN3 0x7304 # define PS_THREAD_PANIC_DISPATCH (3 << 6) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index cc21aca4945..5743fd5b8ae 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -114,6 +114,11 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_load_register_imm32(brw, COMMON_SLICE_CHICKEN3, PS_THREAD_PANIC_DISPATCH_MASK | PS_THREAD_PANIC_DISPATCH); + + /* WaEnableStateCacheRedirectToCS:icl */ + brw_load_register_imm32(brw, SLICE_COMMON_ECO_CHICKEN1, + GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE | + REG_MASK(GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE)); } if (devinfo->gen == 10 || devinfo->gen == 11) { |