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| author | Eduardo Lima Mitev <[email protected]> | 2019-05-12 21:12:59 +0200 |
|---|---|---|
| committer | Eduardo Lima Mitev <[email protected]> | 2019-06-07 08:45:05 +0200 |
| commit | e45de3a6c3380ecffcbfc8034c4b245cc52c7434 (patch) | |
| tree | 85711d538e1eab935f98291a0d8d657751594faa | |
| parent | c27b3758fa0dcd7fade9e85c5483b8310b8263d7 (diff) | |
ir3/compiler: Handle new alu opcodes 'umul_low' and 'imadsh_mix16'
They directly emit ir3_MULL_U and ir3_MADSH_M16 respectively.
Reviewed-by: Eric Anholt <[email protected]>
| -rw-r--r-- | src/freedreno/ir3/ir3_compiler_nir.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index a441eadee84..1a75181a967 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -559,6 +559,12 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) dst[0] = ir3_MUL_S(b, src[0], 0, src[1], 0); } break; + case nir_op_umul_low: + dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0); + break; + case nir_op_imadsh_mix16: + dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0); + break; case nir_op_ineg: dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG); break; |